Datasheet

M16C/6S Group Flash Memory Version
R01DS0201EJ0502 Rev.5.02 page 168 of 203
Dec 25, 2012
Flash memory control register 0
Symbol Address After reset
FMR0 01B7 16 XX000001 2
b7 b6 b5 b4 b3 b2 b1 b0
FMR00
Bit symbol
Bit name Function RW
0: Busy (being written or erased)
1: Ready
CPU rewrite mode select bit
(Note 1)
0: Disables CPU rewrite mode
1: Enables CPU rewrite mode
FMR01
Lock bit disable select bit
(Note 2)
0: Enables lock bit
1: Disables lock bit
Flash memory stop bit
(Note 3, Note 5)
FMR02
FMSTP
00
RY/BY status flag
Reserved bit
Must always be set to “0”
0: Terminated normally
1: Terminated in error
Program status flag (Note 4)
FMR06
0: Terminated normally
1: Terminated in error
Erase status flag (Note 4)
FMR07
Flash memory control register 1
Symbol Address After reset
FMR1 01B5 16 0X00XX0X 2
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Bit name Function
EW1 mode select bit (
Note)
0: EW0 mode
1: EW1 mode
FMR11
0
Reserved bit
Must always be set to “0”
Reserved bit
The value in this bit when read is
indeterminate.
Reserved bit
Must always be set to “0”
000
RW
RW
RW
RW
RO
RO
RO
RW
RO
RW
RW
RW
(b0)
(b5-b4)
(b7)
(b5-b4)
0: Enables flash memory operation
1: Stops flash memory operation
(placed in low power mode,
flash memory initialized)
Note 1: To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or DMA transfers
will occur before writing “1” after writing “0”.
Also, while in EW0 mode, write to this bit from
a program in other than the flash memory.
Note 2: To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Note 3: Write to this bit from a program in other than the flash memory.
Note 4: This flag is cleared to “0” by executing the Clear Status command.
Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMR03 bit
can be set to “1” by writing “1” in a program, the flash memory is neither placed in low power mode
nor initialized.
Reserved bit
The value in this bit when read is
indeterminate.
(b3-b2)
RO
Note : To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
The FMR01 and FMR11 bits both are cleared to “0” by setting the FMR01 bit to “0”.
Nothing is assigned.
When write, set to “0”. When read, their contents are indeterminate.
(b6)
Figure 1.21.1. FIDR Register and FMR0 and FMR1 Registers