Datasheet
M16C/6S Group Flash Memory Version
R01DS0201EJ0502 Rev.5.02 page 164 of 203
Dec 25, 2012
Figure 1.20.3. ROMCP Register
Figure 1.20.4. Address for ID Code Stored
Symbol Address Value when shipped
ROMCP 0FFFFF
16 FF16 (Note 4)
ROM code protect control address
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
00: Removes protect
01:
10:
11:
00:
01:
10:
11: Protect disabled
ROM code protect reset
bit (Note 2, Note 4)
ROM code protect level
1 set bit
(Note 1, Note 3, Note 4)
ROMCR
ROMCP1
b5 b4
b7 b6
11
Reserved bit
Set this bit to “1”
Reserved bit
Set this bit to “1”
Reserved bit
Set this bit to “1”
Reserved bit
Set this bit to “1”
Enables ROOMCP1 bit
}
Protect enabled
}
Note 1: If the ROMCR bits are set to other than ‘002’ and the ROMCP1 bits are set to other than ‘112’ (
ROM code protect enabled), the flash memory is disabled against reading and rewriting in
parallel input/output mode.
Note 2: If the ROMCR bits are set to ‘002’ when the ROMCR bits are other than ‘002’ and the ROMCP1
bits are other than ‘112,’ ROM code protect level 1 is removed. However, because the ROMCR
bits cannot be modified during parallel input/output mode, they need to be modified in standard
serial input/output or other modes.
Note 3: The ROMCP1 bits are effective when the ROMCR bits are ‘012,’ ‘102,’ or ‘112.’
Note 4: Once any of these bits is cleared to “0”, it cannot be set back to “1”. If a memory block that
contains the ROMCP register is erased, the ROMCP register is set to ‘FF16.’
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset vector
Watchdog timer vector
Single step vector
Address match vector
BRK instruction vector
Overflow vector
Undefined instruction vector
ID7
ID6
ID5
ID4
ID3
ID2
ID1
DBC vector
Reserved
0FFFFF
16
to 0FFFFC
16
0FFFFB
16
to 0FFFF8
16
0FFFF7
16
to 0FFFF4
16
0FFFF3
16
to 0FFFF0
16
0FFFEF
16
to 0FFFEC
16
0FFFEB
16
to 0FFFE8
16
0FFFE7
16
to 0FFFE4
16
0FFFE3
16
to 0FFFE0
16
0FFFDF
16
to 0FFFDC
16
4 bytes
Address
ROMCP