Datasheet

M16C/6S Group SI/O3 and SI/O4
R01DS0201EJ0502 Rev.5.02 page 135 of 203
Dec 25, 2012
(a) SI/Oi Operation Timing
Figure 1.17.3 shows the SI/Oi operation timing
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
i= 3, 4
1.5 cycle (max)
SI/Oi internal clock
CLKi output
Signal written to the
SiTRR register
S
OUTi output
S
INi input
SiIC register
IR bit
(Note 2)
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (S
OUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the
rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit = 1 (internal clock), the S
OUTi pin is placed in the high-impedance state after the transfer finishes.
Note 3: If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"1"
"0"
(Note 3)
Figure 1.17.3. SI/Oi Operation Timing
(b) CLK Polarity Selection
The SiC register's SMi4 bit allows selection of the polarity of the transfer clock. Figure 1.17.4 shows
the polarity of the transfer clock.
Figure 1.17.4. Polarity of Transfer Clock
(2) When SiC register's SMi4 bit = “1”
(Note 3)
D 1 D2 D3 D4 D5 D6 D7
D1 D2 D3 D4 D5 D6 D7
D0
D0
SINi
SOUTi
CLKi
(1) When SiC register's SMi4 bit = “0”
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
pin if not transferring data.
Note 3: When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
pin if not transferring data.
D 1 D2 D3 D4 D5 D6 D7D0
D1 D2 D3 D4 D5 D6 D7D0
SINi
SOUTi
CLKi
(Note 2)
i=3 and 4