Datasheet

M16C/6S Group SI/O3 and SI/O4
R01DS0201EJ0502 Rev.5.02 page 133 of 203
Dec 25, 2012
Figure 1.17.2. S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers
SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)
b7 b0
Symbol Address After reset
S3BRG 0363
16 Indeterminate
S4BRG 0367
16 Indeterminate
Description
Assuming that set value = n, BRGi divides the count
source by n + 1
00
16 to FF16
Setting range
RW
SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)
b7 b0
Symbol Address After reset
S3TRR 0360
16 Indeterminate
S4TRR 0364
16 Indeterminate
Description
Transmission/reception starts by writing transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: To receive data, set the corresponding port direction bit for SINi to “0” (input mode).
S I/Oi control register (i = 3, 4) (Note 1)
Symbol Address After reset
S3C 036216 010000016
S4C 036616 010000016
b7 b6 b5 b4 b3 b2 b1 b0
Description
SMi5
SMi1
SMi0
SMi3
SMi6
SMi7
Internal synchronous
clock select bit
Transfer direction select
bit
S I/Oi port select bit
S
OUTi initial value
set bit
0 0 : Selecting f
1SIO or f2SIO
0 1 : Selecting f
8SIO
1 0 : Selecting f
32SIO
1 1 : Must not be set.
b1 b0
0 : External clock
1 : Internal clock
Effective when SMi3 = 0
0 : “L” output
1 : “H” output
0 : Input/output port
1 : S
OUTi output, CLKi function
Bit name
Bit
symbol
Synchronous clock
select bit
0 : LSB first
1 : MSB firs
t
SMi2 SOUTi output disable bit 0 : SOUTi output
1 : S
OUTi output disable(high impedance)
Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit to “1”
(write enable).
Note 2: Set the SMi3 bit to “1” (S
OUTi output, CLKi function).
Note 3: Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
Note 4: Effective when SMi3 bit = 1.
CLK polarity select bit
SMi4
0 : Transmit data is output at falling edge of
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input at
falling edge
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
RW
RW
(Note 4)
(Note 2)
(Note 3)
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.