Datasheet

M16C/6S Group Special Mode
R01DS0201EJ0502 Rev.5.02 page 130 of 203
Dec 25, 2012
• Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3
register’s CKPH bit and the UiC0 register’s CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and salves to be commu-
nicated.
Figure 1.16.6 shows the transmission and reception timing in master (internal clock).
Figure 1.16.7 shows the transmission and reception timing (CKPH=0) in slave (external clock) while
Figure 1.16.8 shows the transmission and reception timing (CKPH=1) in slave (external clock).
Data output timing
Data input timing
D0 D1 D2 D3 D4 D6 D7D5
Clock output
(CKPOL=0, CKPH=0)
"H"
"L"
Clock output
(CKPOL=1, CKPH=0)
"H"
"L"
Clock output
(CKPOL=0, CKPH=1)
"H"
"L"
Clock output
(CKPOL=1, CKPH=1)
"H"
"L"
"H"
"L"
Figure 1.16.6. Transmission and Reception Timing in Master Mode (Internal Clock)