Datasheet
M16C/6S Group SFR
R01DS0201EJ0502 Rev.5.02 page 13 of 203
Dec 25, 2012
SFR
DMA0 control register DM0CON 00000?002
DMA0 transfer counter TCR0 ??
16
??16
DMA1 control register DM1CON 00000?00
2
DMA1 source pointer SAR1 ??
16
??16
X?16
DMA1 transfer counter TCR1 ??
16
??16
DMA1 destination pointer DAR1 ??
16
??16
X?16
Watchdog timer start register WDTS ??
16
Watchdog timer control register WDC 00??????
2
Processor mode register 0 (Note 2) PM0
System clock control register 0 CM0 010010002
System clock control register 1 CM1 00100000
2
Address match interrupt enable register AIER XXXXXX00
2
Protect register PRCR XX0000002
Processor mode register 1 PM1 00XX10X0
2
DMA0 destination pointer DAR0 ??
16
??16
X?16
Note 1: The blank areas are reserved and cannot be used by users.
Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 3: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
X : Nothing is mapped to this bit
? : Undefined
Oscillation stop detection register (Note 3) CM2 0000X0002
Processor mode register 2 PM2 XXX000002
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Address
Register Symbol After reset
Address match interrupt register 0 RMAD0 00
16
0016
X016
Address match interrupt register 1 RMAD1 00
16
0016
X0
16
DMA0 source pointer SAR0 ??
16
??16
X?16
XXXX0X00
2
(CNV
SS
pin is “L”)