Datasheet

M16C/6S Group Special Mode
R01DS0201EJ0502 Rev.5.02 page 129 of 203
Dec 25, 2012
Table 1.16.7. Registers to Be Used and Settings in Special Mode 2
Register Bit Function
UiTB (Note2) 0 to 7 Set transmission data
UiRB (Note2) 0 to 7 Reception data can be read
OER Overrun error flag
UiBRG 0 to 7 Set a transfer rate
UiMR (Note2) SMD2 to SMD0 Set to ‘0012’
CKDIR Set this bit to “0” for master mode or “1” for slave mode
IOPOL Set to “0”
UiC0 CLK1, CLK0 Select the count source for the UiBRG register
CRS Invalid because CRD = 1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Select TxDi pin output format
CKPOL Clock phases can be set in combination with the UiSMR3 register's CKPH bit
UFORM Set to “0”
UiC1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 1) Select UART2 transmit interrupt cause
U2RRM(Note 1), Set to “0”
U2LCH, UiERE
UiSMR 0 to 7 Set to “0”
UiSMR2 0 to 7 Set to “0”
UiSMR3 CKPH Clock phases can be set in combination with the UiC0 register's CKPOL bit
NODC Set to “0”
0, 2, 4 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
UCON U0IRS, U1IRS Select UART0 and UART1 transmit interrupt cause
U0RRM, U1RRM Set to “0”
CLKMD0 Invalid because CLKMD1 = 0
CLKMD1, RCSP, 7 Set to “0”
Note 1: Set the U0C0 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: Not all register bits are described above. Set those bits to “0” when writing to the registers in Special
Mode 2.
i = 0 to 1