Datasheet

M16C/6S Group Special Mode
R01DS0201EJ0502 Rev.5.02 page 123 of 203
Dec 25, 2012
• Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated
when the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the UiSMR register’s BBS bit to determine which interrupt source is requesting the interrupt.
Figure 1.16.3. Detection of Start and Stop Condition
• Output of Start and Stop Condition
A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to “1”
(start).
A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to “1” (start).
A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to “1” (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the UiSMR4 register to “1” (output).
The function of the STSPSEL bit is shown in Table 1.16.5 and Figure 1.16.4.
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
i = 0 to 2
Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number of
f
1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.
Duration for
setting up
Duration for
holding
SCLi
SDAi
(Start condition)
SDA i
(Stop condition)