Datasheet

M16C/6S Group Special Mode
R01DS0201EJ0502 Rev.5.02 page 122 of 203
Dec 25, 2012
Figure 1.16.2. Transfer to UiRB Register and Interrupt Timing
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
i=0 to 2
This diagram applies to the case where the following condition is met.
• UiMR register CKDIR bit = 0 (Slave selected)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
Receive interrupt
(DMA1 request)
Transmit interrupt
Transfer to UiRB register
(4) IICM2= 1, CKPH= 1
D6 D5 D4 D3 D2 D1
D7
SDAi
SCLi
D0
D6 D5 D4 D3 D2 D1
D7
SDAi
SCLi
D0
D6 D5 D4 D3 D2 D1 D8 (ACK, NACK)
D7
SDAi
SCLi
D0
D8 (ACK, NACK)
D
8 (ACK, NACK)
D6 D5 D4 D3 D2 D1 D8 (ACK, NACK)
D7
SDAi
SCLi
D0
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
b15
•••
b9 b8 b7 b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
b15
•••
b9 b8 b7 b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
b15
•••
b9 b8 b7 b0
D0 D7 D6 D5 D4 D3 D2 D1
b15
•••
b9 b8 b7 b0
D0 D7 D6 D5 D4 D3 D2 D1
b15
•••
b9 b8 b7 b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
(2) IICM2= 0, CKPH= 1 (clock delay)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
UiRB register
Transmit interrupt
Transfer to UiRB register
Receive interrupt
(DMA1 request)
Transfer to UiRB register
UiRB register
UiRB register
UiRB register