Datasheet

M16C/6S Group Special Mode
R01DS0201EJ0502 Rev.5.02 page 120 of 203
Dec 25, 2012
UiSMR4 STAREQ Set this bit to “1” to generate start Set to “0”
condition
RSTAREQ Set this bit to “1” to generate restart Set to “0”
condition
STPREQ Set this bit to “1” to generate stop Set to “0”
condition
STSPSEL Set this bit to “1” to output each condition Set to “0”
ACKD Select ACK or NACK Select ACK or NACK
ACKC Set this bit to “1” to output ACK data Set this bit to “1” to output ACK data
SCLHI Set this bit to “1” to have SCLi output Set to “0”
stopped when stop condition is detected
SWC9 Set to “0” Set this bit to “1” to set the SCLi to “L”
hold at the falling edge of the 9th bit of
clock
IFSR2A IFSR26, ISFR27 Set to “1” Set to “1”
UCON U0IRS, U1IRS Invalid Invalid
2 to 7 Set to “0” Set to “0”
Register Bit Function
Master Slave
Table 1.16.3. Registers to Be Used and Settings in I
2
C Mode (2) (Continued)
i=0 to 2