Datasheet

M16C/6S Group Special Mode
R01DS0201EJ0502 Rev.5.02 page 118 of 203
Dec 25, 2012
CLK
control
Falling edge
detection
External
clock
Internal clock
Start/stop condition detection
interrupt request
Start condition
detection
Stop condition
detection
Reception register
Bus
busy
Transmission
register
Arbitration
Noise
Filter
SDAi
SCLi
UARTi
D
T
Q
D
T
Q
D
T
Q
NACK
AC
K
UARTi
UARTi
UARTi
R
UARTi transmit,
NACK interrupt
request
UARTi receive,
ACK interrupt request,
DMA1 reques
t
IICM=1 and
IICM2=0
S
R
Q
ALS
R
S
SWC
IICM=1 and
IICM2=0
IICM2=1
IICM2=1
SWC2
SDHI
DMA0, DMA1 request
(UART1: DMA0 only
)
Noise
Filter
i=0 to
2
IICM=0
IICM=
1
DMA0
(UART0, UART2)
STPSEL=0
STPSEL=1
STPSEL=1
STPSEL=0
SDA
STSP
SCLSTSP
ACK=1 ACK=0
Q
Port register
(Note)
I/O port
9th bit falling edge
9th bit
ACKD register
Delay
circuit
This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 010
2 and the UiSMR register's IICM bit = 1.
Note: When the IICM bit =1, the pins can be read even if the direction bit = 1 (output).
Start and stop condition generation bloc
k
IICM : Bit in UiSMR register
IICM2, SWC, ALS, SWC2, SDHI : Bit in UiSMR2 register
STSPSEL, ACKD, ACKC : Bit in UiSMR4 register
Figure 1.16.1. I
2
C Mode Block Diagram