Datasheet

M16C/6S Group Special Mode
R01DS0201EJ0502 Rev.5.02 page 117 of 203
Dec 25, 2012
Special Mode 1 (I
2
C mode)
I
2
C mode is provided for use as a simplified I
2
C interface compatible mode. Table 1.16.1 lists the speci-
fications of the I
2
C mode. Table 1.16.2 lists the registers used in the I
2
C mode and the register values
set. Figure 1.16.1 shows the block diagram for I
2
C mode. Figure 1.16.2 shows SCLi timing.
As shown in Table 1.16.4, the microcomputer is placed in I
2
C mode by setting the SMD2 to SMD0 bits to
‘0102’ and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output
does not change state until SCLi goes low and remains stably low.
Table 1.16.1. I
2
C Mode Specifications
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • During master
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• During slave
CKDIR bit = “1” (external clock) : Input from CLKi pin
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_
The TE bit of UiC1 register= 1 (transmission enabled)
_
The TI bit of UiC1 register = 0 (data present in UiTB register)
Reception start condition • Before reception can start, the following requirements must be met (Note 1)
_
The RE bit of UiC1 register= 1 (reception enabled)
_
The TE bit of UiC1 register= 1 (transmission enabled)
_
The TI bit of UiC1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Error detection • Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the data
Select function • Arbitration lost
Timing at which the UiRB register’s ABT bit is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the
high state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC
register does not change .
Interrupt request
generation timing