Datasheet

M16C/6S Group UART Mode
R01DS0201EJ0502 Rev.5.02 page 113 of 203
Dec 25, 2012
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
Figure 1.15.2. Receive Operation
D 0
Start bit
Sampled “L”
UiBRG count
source
RxDi
Transfer clock
RTSi
Stop bit
“1”
“0”
“0”
“1”
“H”
“L”
“0”
“1”
Reception triggered when transfer clock
is generated by falling edge of start bit
UiC1 register
RE bit
UiC1 register
RI bit
SiRIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Receive data taken in
D 7
D 1
Transferred from UARTi receive
register to UiRB register
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2
Table 1.15.5. Example of Bit Rates and Settings
etaRtiB
)spb(
ecruoStnuoC
GRBfo
zHM61:kcolCnoitcnuFlarehpireP
zHM42:kcolCnoitcnuFlarehpireP
n:GRBfoeulaVteS)spb(emiTlautcAn:GRBfoeulavteS)spb(emiTlautcA
00218f)h76(3012021)h69(5512021
00428f)h33(154042)h64(774042
00848f)h91(528084)h62(838084
00691f)h76(3015169)h69(5515169
004411f)h44(8639441)h76(30132441
002911f)h33(1513291)h64(7713291
008821f)h22(4317582)h33(1564882
052131f)hF1(1305213)hF2(7405213
004831f)h91(5226483)h62(8326483
002151f)h31(9100005)hC1(8242715
Bit Rates
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 1.15.5 lists example of bit rates and settings.