Datasheet
M16C/6S Group UART Mode
R01DS0201EJ0502 Rev.5.02 page 110 of 203
Dec 25, 2012
Table 1.15.2. Registers to Be Used and Settings in UART Mode
Register Bit Function
UiTB 0 to 8 Set transmission data (Note 1)
UiRB 0 to 8 Reception data can be read (Note 1)
OER,FER,PER,SUM
Error flag
UiBRG 0 to 7 Set a transfer rate
UiMR SMD2 to SMD0 Set these bits to ‘100
2’ when transfer data is 7 bits long
Set these bits to ‘1012’ when transfer data is 8 bits long
Set these bits to ‘1102’ when transfer data is 9 bits long
CKDIR Select the internal clock or external clock
STPS Select the stop bit
PRY, PRYE Select whether parity is included and whether odd or even
IOPOL Select the TxD/RxD input/output polarity
UiC0 CLK0, CLK1 Select the count source for the UiBRG register
CRS
_______ _______
Select CTS or RTS to use
TXEPT Transmit register empty flag
CRD
_______ _______
Enable or disable the CTS or RTS function
NCH Select TxDi pin output mode (Note 2)
CKPOL Set to “0”
UFORM LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
bit to “0” when transfer data is 7 or 9 bits long.
UiC1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 2) Select the source of UART2 transmit interrupt
U2RRM (Note 2) Set to “0”
UiLCH Set this bit to “1” to use inverted data logic
UiERE Set to “0”
UiSMR 0 to 7 Set to “0”
UiSMR2 0 to 7 Set to “0”
UiSMR3 0 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set to “0”
CLKMD0 Invalid because CLKMD1 = 0
CLKMD1 Set to “0”
RCSP
_________
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7 Set to “0”
Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long;
bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are included in the UCON register.
Note 3: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
i=0 to 2