Datasheet

M16C/6S Group Clock Synchronous serial I/O Mode
R01DS0201EJ0502 Rev.5.02 page 107 of 203
Dec 25, 2012
(e) Transfer Clock Output From Multiple Pins (UART1)
Use the UCON register’s CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins.
(See Figure 1.14.5.) This function can be used when the selected transfer clock for UART1 is an
internal clock.
Figure 1.14.5. Transfer Clock Output From Multiple Pins
Microcomputer
TXD1 (P67)
CLKS
1 (P64)
CLK
1 (P65)
IN
CLK
IN
CLK
Note: This applies to the case where the U1MRregister's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1 (
transfer clock out
p
ut from multi
p
le
p
ins
)
.
Transfer enabled
when the UCON
register's
CLKMD0 bit = 0
Transfer enabled
when the UCON
register's
CLKMD0 bit = 1
Figure 1.14.4. Serial Data Logic Switching
D0 D1 D2 D3 D4 D5 D6 D7
Transfer clock
TxD
i
(no reverse)
“H”
“L”
“H”
“L”
TxD i
(reverse)
D0 D1 D2 D3 D4 D5 D6 D7
“H”
“L”
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock
“H”
“L”
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
i = 0 to 1