Datasheet

M16C/6S Group Clock Synchronous serial I/O Mode

R01DS0201EJ0502 Rev.5.02 page 106 of 203

Dec 25, 2012

In continuous receive mode, receive operation becomes enable when the receive buffer register is

read. It is not necessary to write dummy data into the transmit buffer register to enable receive

operation in this mode. However, a dummy read of the receive buffer register is required when start-

ing the operation mode.

When the UiRRM bit (i = 0 to 1) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “1”

(data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not

write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON

(d) Serial Data Logic Switching Function

When the UiC1 register (i = 0 to 1)’s UiLCH bit = 1 (reverse), the data written to the UiTB register has

its logic reversed before being transmitted. Similarly, the received data has its logic reversed when

read from the UiRB register.

Figure 1.14.4 shows serial data logic.

(b) LSB First/MSB First Select Function

Use the UiC0 register (i = 0 to 1)’s UFORM bit to select the transfer format. Figure 1.14.3 shows the

transfer format.

Figure 1.14.3. Transfer Format

(1) When UiC0 register's UFORM bit = 0 (LSB first)

D1 D2 D3 D4 D5 D6 D7

TXDi

RXDi

CLKi

(2) When UiC0 register's UFORM bit = 1 (MSB first)

D6 D5 D4 D3 D2 D1 D0

TXDi

RXDi

CLKi

Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (

transmit data output at the falling edge and the receive data taken

in at the rising edge of the transfer clock) and the UiC1 register’s

UiLCH bit = 0 (no reverse).

i = 0 to 1