Datasheet

M16C/6S Group Clock Synchronous serial I/O Mode
R01DS0201EJ0502 Rev.5.02 page 103 of 203
Dec 25, 2012
Table 1.14.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
1.14.3 shows pin functions for the case where the multiple transfer clock output pin select function is
deselected. Table 1.14.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that
for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs
an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)
Table 1.14.3. Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name Function Method of selection
TxDi (i = 0 to 2)
(P6
3, P67)
Serial data output
Serial data input
Transfer clock output
Transfer clock input
I/O port
(Outputs dummy data when performing reception only)
RxDi
(P6
2, P66)
CLKi
(P6
1, P65)
UiMR register’s CKDIR bit=0
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0
PD6 register’s PD6_2 bit=0, PD6_6 bit=0
(Can be used as an input port when performing transmission only)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
UiC0 register’s CRD bit=1
CTS input
RTS output
CTSi/RTSi
(P6
0, P64)
Table 1.14.4. P64 Pin Functions
Pin function Bit set value
U1C0 register
UCON register PD6 register
CRD
CRS
RCSP
CLKMD1
CLKMD0 P
D6_4
P6
4 100 Input: 0, Output: 1
CTS
1
000 0
RTS
1
10 0
CTS
0 (Note1)
0
CLKS
1
0
0
00
1(Note 2
)1
Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS
0 /RTS 0 enabled) and the U0
C0 register’s CRS bit to “1” (RTS
0 selected).
Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the U1C0 register’s CLKPOL bit = 0
• Low if the U1C0 register’s CLKPOL bit = 1
1
0