M16C/6S Group R01DS0201EJ0502 Rev.5.02 Dec 25, 2012 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview The M16C/6S group are highly integrated single-chip microcomputers with PLC (Power Line Communication) modem core and AFE (Analog Front End) in a 64-pin plastic molded LQFP package, which incorporates IT800 PLC modem technology developed by Yitran Communications Ltd. M16C/60 Series CPU core enables a high level of code efficiency and high-speed operation.
M16C/6S Group Overview Performance Outline Table 1.1.1 lists performance outline of M16C/6S group. Table 1.1.1. Performance outline of M16C/6S group CPU Item Number of basic instructions Minimum Instruction Execution time Operation Mode Memory Space Memory Capacity ROM RAM Port Multifunction Timer Serial I/O Performance 91 instructions 65.1 ns (f(BCLK)= 15.36MHZ, VCC= 3.0V to 3.6V) Single-chip mode 1M Byte See Tables 1.1.3 and 1.1.
M16C/6S Group Overview IT800 PHY performance outline of M16C/6S group. The IT800 PHY is a PLC optimized Physical Layer (PHY) which consists of IT800 modem core and internal AFE (Analog Front End). The implementation of Yitran's patented DCSK spread spectrum modulation technique in the IT800 modem core enables extremely robust communication over the existing electrical wiring, with data rates up to 7.5Kbps.
1 XOUT 5.12MHz XIN M16C Core A0 FB SB R0L R1L nCD1 nCD0 P56 P54 P53 RAM SI1 SI3 CLK_IN 46.08MHz SI2 EXTCLK 15.
M16C/6S Group Overview Product List Tables 1.1.3 and 1.1.4 list the M16C/6S group product and Figure 1.1.2 shows the type numbers, memory sizes and packages. Table 1.1.3. Product List (1) M16C/6S Type No. M306S0FAGP ROM capacity RAM capacity 96K bytes 24K bytes Current of Dec. 2012 Package type Remarks PLQP0064KB-A (64P6Q-A) Flash memory Product Code U3, U5 Table 1.1.4. Product List (2) M16C/6S D-version Current of Dec.
M16C/6S Group Overview Table 1.1.5. Product Code (1) M16C/6S Internal ROM Product Code U3 Package LEAD free U5 E/W cycles Temperature range 100 0°C to 60°C Microcomputer operating temperature -40°C to 85°C -20°C to 85°C Table 1.1.6.
M16C/6S Group Overview Pin Configuration Figures 1.1.4 show the pin configurations (top view).
M16C/6S Group Overview Table 1.1.7 Pin Description (1) Pin name VCC, VSS Signal name Power supply input I/O type CNVSS CNVSS Input RESET XIN Reset input Clock input Input Input XOUT Clock output Output VCCA Function Apply 3.0V to 3.6V to the VCC pin. Apply 0V to the VSS pin. This is a pin for changing flash memory mode. Usually, connect to VSS. “L” on this input resets the microcomputer. I/O pins for the main clock generation circuit.
M16C/6S Group Overview Table 1.1.8 Pin Description (2) (Analog pin) Pin name Function I/O type PRE-BOUT Output This is a pre-amp buffer output. PRE-INN Input This is a pre-amp differential signal input. PRE-INP Input This is a pre-amp differential signal input. VREF Input This is the reference voltage input of amplifier common to channels 1, 2, and 3. VDCCN Input This is a pin for a test. Usually, please carry out a pull-up. AMP1-IN Input This is a channel 1 amplifier input.
M16C/6S Group Memory Memory Figure 1.2.1 is a memory map of the M16C/6S group. The address space extends the 1M bytes from address 0000016 to FFFFF16. The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example, a 96-Kbyte internal ROM is allocated to the addresses from E800016 to FFFFF16. The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store the start address of each interrupt routine here.
M16C/6S Group Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 1.3.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
M16C/6S Group Central Processing Unit (CPU) (3) Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. (4) Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. (5) Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed.
M16C/6S Group SFR SFR Register Address Symbol After reset 000016 000116 000216 000316 000416 000516 000616 000716 Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 (Note 2) PM0 PM1 CM0 CM1 XXXX0X002 (CNVSS pin is “L”) 00XX10X02 010010002 001000002 000816 AIER PRCR XXXXXX002 XX0000002 CM2 0000X0002 Watchdog timer start register Watchdog timer control register Address match interrupt register 0 WDTS WDC RMAD0 ??16 00??????2 0
M16C/6S Group SFR Register Symbol After reset INT3 interrupt control register INT3IC XX00?0002 UART1 BUS collision detection interrupt control register UART0 BUS collision detection interrupt control register SI/O4 interrupt control register (S4IC) SI/O3 interrupt control register UART2 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register U1BCNIC U0BCNIC S4IC S3IC BCNIC DM0IC DM1IC XXXX?0002 XXXX?0002 XX00?0002 XX00?0002 XXXX?0002 XXXX?
M16C/6S Group SFR Register Address Symbol After reset 008016 008116 008216 008316 008416 008516 008616 ~ ~ 01B016 01B116 01B216 01B316 01B416 Flash memory control register 1 FMR1 0?00??0?2 Flash memory control register 0 Address match interrupt register 2 FMR0 RMAD2 01BB16 Address match interrupt enable register 2 01BC16 Address match interrupt register 3 AIER2 RMAD3 ??0000012 0016 0016 X016 XXXXXX002 0016 0016 X016 01B516 01B616 01B716 01B816 01B916 01BA16 01BD16 01BE16 01BF16 ~ ~ 02
M16C/6S Group Address SFR Register Symbol After reset 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 Interrupt cause select register 2 Interrupt cause select register SI/O3 transmit/receive register IFSR2A IFSR S3TRR 00XXXXXX2 0016 ??16 SI/O3 control register SI/O3 bit rate generator SI/O4 transmit/receive register
M16C/6S Group SFR Count start flag Register Symbol TABSR After reset 0016 One-shot start flag Trigger select register Up-down flag ONSF TRGSR UDF 0016 0016 0016 Timer A0 register TA0 Timer A1 register TA1 Timer A2 register TA2 Timer A3 register TA3 Timer A4 register TA4 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register TA0MR TA1MR TA2MR TA3MR TA4MR 0016 0016 0016 0016 0016
M16C/6S Group Address SFR Register Symbol After reset 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 Port P1 register P1 ??16 Port P1 direction register PD1 0016 Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction regist
M16C/6S Group Reset Reset There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscillation stop detection reset. Hardware Reset ____________ ____________ A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power supply voltage is within the recommended operating condition, the pins are initialized (see Table 1.5.1). The oscillation circuit is initialized and the main clock starts oscillating.
M16C/6S Group Reset Software Reset When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset vector. Select the main clock for the CPU clock source, and set the PM03 bit to “1” with main clock oscillation satisfactorily stable. At software reset, some SFR’s are not initialized. Refer to “SFR”.
M16C/6S Group Reset VCC1 XIN td(P-R) More than 20 cycles are needed RESET BCLK 28cycles BCLK Single chip mode Internal address FFFFC16 Content of reset vector FFFFE16 Figure 1.5.2. Reset Sequence R01DS0201EJ0502 Rev.5.
M16C/6S Group Reset ____________ Table 1.5.1.
M16C/6S Group Processor Mode Processor Mode (1) Setting Processor Modes Processor mode is available only: single-chip mode. Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register. Table 1.6.1 shows the processor mode after hardware reset. Table 1.6.2 shows the PM01 to PM00 bits set values and processor modes. For setting Single-chip mode. CNVss should be kept Vss level. And PM01 to PM00 of PM0 register should be set "00." Table 1.6.1.
M16C/6S Group Processor Mode (2) Setting PLC Mode PLC mode is simply set by putting P15 High level during RESET. TR RESET P15 Tsetup THOLD Figure 1.6.1. PLC mode by P15 simply setting Table 1.6.3. RESET and P15 Input min TR 40us Tset up 5us THOLD 5us R01DS0201EJ0502 Rev.5.
M16C/6S Group Processor Mode Processor mode register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PM0 Address 000416 Bit symbol PM00 Bit name Processor mode bit (Note 2) PM01 (b2) PM03 (b7-b4) After reset (Note 2) XXXX0X002 (CNVSS pin = “L”) Function RW b1 b0 RW 0 0: Single-chip mode 0 1: Must not be set 1 0: Must not be set 1 1: Must not be set RW Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.
M16C/6S Group Processor Mode Single-chip mode 0000016 SFR 0040016 Internal RAM XXXXX16 PM13=1 (Note1) Internal RAM Capacity Address XXXXX16 Can not use 24K bytes 063FF16 Internal ROM Capacity Address YYYYY16 64K bytes F000016 96K bytes E800016 YYYYY16 Internal ROM FFFFF16 Note 1: Since internal RAM which can be used becomes 15 K bytes when PM13 is “0”, please be sure to set PM13 to “1”. Figure 1.6.4. Memory Map in Single Chip Mode R01DS0201EJ0502 Rev.5.
M16C/6S Group Clock Generation Circuit Clock Generation Circuit The clock generation circuit contains two oscillator circuits as follows: (1) Main clock oscillation circuit (2) On-chip Oscillator (oscillation stop detect function) Table 1.7.1 lists the clock generation circuit specifications. Figure 1.7.1 shows the clock generation circuit. Figures 1.7.2 to 1.7.5 show the clock-related registers. Table 1.7.1.
M16C/6S Group Clock Generation Circuit f1 PCLK0=1 f2 XIN PCLK0=0 XOUT f8 5.12MHz CM21 Standard serial I/O mode (5.12MHz) On-chip oscillator On-chip oscillator clock f32 fAD 46.08MHz PLL Oscillation stop, reoscillation detection circuit 1/3 Normal operation mode IT800 CLK_IN (15.
M16C/6S Group Clock Generation Circuit System clock control register 0 (Notes 1 and 4) b7 0 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 0 Bit symbol Address 000616 After reset 010010002 Bit name Function (b1-b0) Nothing is assigned. When write, set to “0”. When read, its content is indeterminate. CM02 WAIT peripheral function clock stop bit (Note 3) (b4-b3) Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.
M16C/6S Group Clock Generation Circuit System clock control register 1 (Note 1) b7 b6 b5 b4 1 0 0 b3 b2 b1 b0 Symbol CM1 0 0 Bit symbol CM10 (b4-b1) (b5) CM16 CM17 Address 000716 After reset 001000002 Bit Function RW name All clock stop control bit (Notes 3, 4) 0 : Clock on 1 : All clocks off (stop mode) RW Reserved bit Must set to “0” RW Must set to “1” RW Reserved bit Main clock division select bit 1 (Note 2) b7 b6 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Divisi
M16C/6S Group Clock Generation Circuit Oscillation stop detection register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol CM2 Bit symbol CM20 CM21 CM22 CM23 (b5-b4) (b6) Address 000C16 After reset 0X0000002(Note 10) Bit name Function RW Oscillation stop, reoscillation detection bit (Notes 7, 8, 9, 10) 0: Oscillation stop, re-oscillation detection function disabled 1: Oscillation stop, re-oscillation detection function enabled RW System clock select bit 2 (Notes 2, 3, 6, 10) 0: Main clo
M16C/6S Group Clock Generation Circuit Peripheral clock select register (Note) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 Symbol PCLKR Address 025E16 Bit symbol Bit name PCLK0 Timers A, B clock select bit (Clock source for the timers A, B, and the dead time timer) PCLK1 (b7-b2) When reset 000000112 Function RW 0 : f2 1 : f1 RW SI/O clock select bit (Clock source for UART0 to UART2, SI/O3, SI/O4) 0 : f2SIO 1 : f1SIO RW Reserved bit Must set to “0” RW Note: Write to this register after
M16C/6S Group Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. (1) Main Clock Main clock is supplied by IT800 with a tripled clock of XIN (main clock oscillator). This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor.
M16C/6S Group Clock Generation Circuit (3) On-chip Oscillator Clock This clock, approximately 1 MHz, is supplied by a On-chip Oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit of PM2 register is “1” (Onchip Oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer. After reset, the On-chip Oscillator clock is turned off.
M16C/6S Group Clock Generation Circuit CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions. (1) CPU Clock and BCLK These are operating clocks for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, or On-chip Oscillator clock.
M16C/6S Group Clock Generation Circuit Power Control There are three power control modes. For convenience’ sake, all modes other than wait and stop modes are referred to as normal operation mode here. (1) Normal Operation Mode Normal operation mode is further classified into three modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency.
M16C/6S Group Clock Generation Circuit Table 1.7.2.
M16C/6S Group Clock Generation Circuit Table 1.7.3. Pin Status During Wait Mode Pin Status Retains status before wait mode I/O ports Table 1.7.4.
M16C/6S Group Clock Generation Circuit (3) Stop Mode In stop mode, all the M16C core's internal oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. However, the peripheral functions clocked by external signals keep operating. The following interrupts can be used to exit stop mode.
M16C/6S Group Clock Generation Circuit Table 1.7.5. Pin Status in Stop Mode Pin I/O ports R01DS0201EJ0502 Rev.5.
M16C/6S Group Clock Generation Circuit Figure 1.7.7 shows the state transition from normal operation mode to stop mode and wait mode.
M16C/6S Group Clock Generation Circuit Main clock oscillation On-chip Oscillator clock oscillation High-speed mode CPU clock: f(XIN) Middle-speed mode (divide by 2) CPU clock: f(XIN)/2 Middle-speed mode (divide by 4) CPU clock: f(XIN)/4 CM07=0 CM07=0 CM07=0 CM06=0 CM06=0 CM06=0 CM17=0 CM17=0 CM17=1 CM16=0 CM16=1 CM16=0 Middle-speed mode Middle-speed mode (divide by 8) (divide by 16) CPU clock: f(XIN)/8 CM07=0 CM06=1 CPU clock: f(XIN)/16 On-chip Oscillator mode CM21=0 (Note 4) CM07=0 CM0
M16C/6S Group Clock Generation Circuit Table 1.7.6. Allowed Transition and Setting State after transition High-speed mode, On-chip Oscillator middle-speed mode mode Current state Stop mode See Table A (7) (8)1 On-chip Oscillator mode (6)2 See Table A (8)1 Stop mode (10)3 (10)3 (10) (10) High-speed mode, middle-speed mode Wait mode Wait mode (9) (9) -- ---: Cannot transit Table 1. State Transition with Main Clock Division Ration in High- or Middle-speed Mode and On-chip Oscillator Mode.
M16C/6S Group Clock Generation Circuit System Clock Protective Function When the main clock is selected for the CPU clock source, this function disables the clock against modifications in order to prevent the CPU clock from becoming halted by run-away.
M16C/6S Group Clock Generation Circuit Oscillation Stop and Re-oscillation Detect Function The oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and reoscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation detection interrupt are generated. Which is to be generated can be selected using the CM27 bit of CM2 register. Main clock oscillator of M16C/6S does not stop even if Xin input stops.
M16C/6S Group Protection Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 1.8.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
M16C/6S Group Interrupts Interrupts Type of Interrupts Figure 1.9.1 shows types of interrupts.
M16C/6S Group Interrupts Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation resulted in an overflow).
M16C/6S Group Interrupts Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. (1) Special Interrupts Special interrupts are non-maskable interrupts. ________ • DBC Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools. • Watchdog Timer Interrupt Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer.
M16C/6S Group Interrupts Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 1.9.2 shows the interrupt vector. MSB Vector address (L) LSB Low address Mid address Vector address (H) 0000 High address 0000 0000 Figure 1.9.2.
M16C/6S Group Interrupts • Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 1.9.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses. Table 1.9.2.
M16C/6S Group Interrupts Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 1.9.
M16C/6S Group Interrupts Interrupt control register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U1BCNIC (Note 3) U0BCNIC (Note 3) BCNIC DM0IC, DM1IC S0TIC to S2TIC S0RIC to S2RIC TA0IC to TA4IC Bit symbol ILVL0 Address 0046 16 0047 16 004A16 004B16, 004C16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 Bit name Interrupt priority level select bit ILVL1 ILVL2 IR (b7-b4) Interrupt request bit After reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 Fun
M16C/6S Group Interrupts I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts. IR Bit The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to “0” (= interrupt not requested).
M16C/6S Group Interrupts Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
M16C/6S Group Interrupts Interrupt Response Time Figure 1.9.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed ((a) in Figure 1.9.
M16C/6S Group Interrupts Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 1.9.6 shows the stack status before and after an interrupt request is accepted.
M16C/6S Group Interrupts The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP(Note), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (Note) is even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 1.9.7 shows the operation of the saving registers.
M16C/6S Group Interrupts Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
M16C/6S Group Interrupts Priority level of each interrupt Level 0 (initial value) INT1 High Timer A3 Timer A1 UART1 bus collision INT3 INT2 INT0 Timer A4 Timer A2 UART0 bus collision UART1 reception, ACK1 UART0 reception, ACK0 Priority of peripheral function interrupts (if priority levels are same) UART2 reception, ACK2 DMA1 UART 2 bus collision SI/O4 Timer A0 UART1 transmission, NACK1 UART0 transmission, NACK0 UART2 transmission, NACK2 DMA0 Low SI/O3 IPL I flag Address match Interrupt request lev
M16C/6S Group Interrupts ______ INT Interrupt _______ INTi interrupt (i=0 to 3) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR register's IFSRi bit. Figure 1.9.10 shows the IFSR and IFSR2A registers.
M16C/6S Group Interrupts Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi register. Use the AIER register’s AIER0 and AIER1 bits and the AIER2 register’s AIER20 and AIER21 bits to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
M16C/6S Group Interrupts Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit symbol Address 000916 After reset XXXXXX002 Function RW AIER0 Address match interrupt 0 enable bit Bit name 0 : Interrupt disabled 1 : Interrupt enabled RW AIER1 Address match interrupt 1 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW (b7-b2) Nothing is assigned. When write, set to “0”. When read, their contents are indeterminate.
M16C/6S Group Interrupts Precautions for Interrupts (1) Reading Address 0000016 • Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
M16C/6S Group Interrupts (5) Modifying Interrupt Control Register • Each interrupt control register can only be modified while no interrupt requests corresponding to that register are generated. If interrupt requests managed by any interrupt control register are likely to occur, disable the interrupts before modifying the register. A sample program is shown below. To modify any interrupt control register after disabling interrupts, be careful with the instructions used.
M16C/6S Group Watchdog Timer Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.
M16C/6S Group Watchdog Timer Setting the PM22 bit to “1” results in the following conditions • The On-chip Oscillator starts oscillating, and the On-chip Oscillator clock becomes the watchdog timer count source. Watchdog timer count (32768) Watchdog timer period = on-chip oscillator clock • The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode entered.) • The watchdog timer does not stop when in wait mode.
M16C/6S Group DMAC DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address. The DMAC uses the same data bus as used by the CPU.
M16C/6S Group DMAC Table 1.11.1. DMAC Specifications Item No. of channels Transfer memory space Maximum No.
M16C/6S Group DMAC DMA0 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Address 03B816 Bit symbol DSEL0 DSEL1 After reset 0016 Function Bit name DMA request cause select bit Refer to note RW DSEL2 RW DSEL3 (b5-b4) DMS RW RW RW Nothing is assigned. When write, set to “0”. When read, its content is “0”.
M16C/6S Group DMAC DMA1 request cause select register b7 b6 b5 b4 b3 b2 b1 Symbol DM1SL b0 Address 03BA16 DSEL1 DSEL2 Function Bit name Bit symbol DSEL0 After reset 0016 DMA request cause select bit RW Refer to note RW RW DSEL3 (b5-b4) DMS RW RW Nothing is assigned. When write, set to “0”. When read, its content is “0”.
M16C/6S Group DMAC DMAi source pointer (i = 0, 1) (Note) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 002216 to 002016 003216 to 003016 Function Set the source address of transfer After reset Indeterminate Indeterminate Setting range RW 0000016 to FFFFF16 RW Nothing is assigned. When write, set “0”. When read, these contents are “0”.
M16C/6S Group DMAC 1. Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination ________ addresses of transfer. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.
M16C/6S Group DMAC (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address BCLK Address bus CPU use Dummy cycle Destination Source CPU use RD signal WR signal Data bus CPU use Dummy cycle Destination Source CPU use (2) When the transfer unit is 16 bits and the source address of transfer is an odd address BCLK Address bus CPU use Source Source + 1 Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source + 1 Source Destination Dumm
M16C/6S Group DMAC 2. DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the number of DMA transfer cycles. Table 1.11.3 shows the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 1.11.2.
M16C/6S Group DMAC 3. DMA Enable When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register is “1” (forward) or the DARi register value when the DAD bit of DMiCON register is “1” (forward). (2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
M16C/6S Group DMAC 5. Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA requests are arbitrated according to the channel priority, DMA0 > DMA1.
M16C/6S Group Timers Timers Five 16-bit timers, each capable of operating independently of the others. The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. Figures 1.12.1 show block diagrams of timer A.
M16C/6S Group Timer A Timer A Figure 1.12.2 shows a block diagram of the timer A. Figures 1.12.3 to 1.12.5 show registers related to the timer A. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode. • Timer mode: The timer counts an internal count source.
M16C/6S Group Timer A Timer Ai register (i= 0 to 4) (Note 1) (b15) b7 (b8) b0 b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Address 038716, 038616 038916, 038816 038B16, 038A16 038D16, 038C16 038F16, 038E16 After reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Setting range RW Timer mode Event counter mode Divide the count source by n + 1 where n = set value 000016 to FFFF16 RW Divide the count source by FFFF16 – n + 1 where n = set value when counting up or by n + 1 when countin
M16C/6S Group Timer A One-shot start flag b7 b6 b5 b4 b3 b2 b1 Symbol ONSF b0 Address 038216 After reset 0016 0 Bit symbol Bit name Function RW TA0OS Timer A0 one-shot start flag RW TA1OS Timer A1 one-shot start flag The timer starts counting by setting this bit to “1” while the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) = ‘102’ (= one-shot timer mode) and the MR2 bit of TAiMR register = “0” (=TAiOS bit enabled). When read, its content is “0”. Should be set to “0”.
M16C/6S Group Timer A 1. Timer Mode In timer mode, the timer counts a count source generated internally (see Table 1.12.1). Figure 1.12.6 shows TAiMR register in timer mode. Table 1.12.1.
M16C/6S Group Timer A 2. Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timer A4 can count two-phase external signals. Table 1.12.2 lists specifications in event counter mode (when not processing two-phase pulse signal). Table 1.12.3 lists specifications in event counter mode (when processing two-phase pulse signal with the timer A4). Figure 1.12.
M16C/6S Group Timer A Timer Ai mode register (i=0 to 4) (When not using two-phase pulse signal processing) b7 b6 b5 0 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR 0 1 Address 039616 to 039A16 Bit symbol Bit name TMOD0 Operation mode select bit Function RW R W RW RW b1 b0 0 1 : Event counter mode (Note 1) TMOD1 MR0 After reset 0016 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin functions as I/O port) 1 : Pulse is output (Note 2) RW (TAiOUT pin functions as pulse outpu
M16C/6S Group Timer A Table 1.12.3 shows the Specifications in event counter mode (when processing two-phase pulse signal with timer A4), and Figure 1.12.8 shows the TA4MR registers in event counter mode (when using twophase pulse signal processing with timer A4). Table 1.12.3.
M16C/6S Group Timer A Timer Ai Mode Register (i=4) (When Using Two-Phase Pulse Signal Processing) b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 1 Symbol TA4MR Bit Symbol TMOD0 Address 039Ah Function RW 0 1 : Event counter mode RW RW Bit Name Operation Mode Select Bit TMOD1 MR0 After Reset 00h b1 b0 To use two-phase pulse signal processing, set this bit to “0”. RW To use two-phase pulse signal processing, set this bit to “0”.
M16C/6S Group Timer A 3. One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. (See Table 1.12.4.) When the trigger occurs, the timer starts up and continues operating for a given period. Figure 1.12.9 shows the TAiMR register in one-shot timer mode. Table 1.12.4.
M16C/6S Group Timer A Timer Ai mode register (i=0 to 4) b7 b6 b5 0 b4 b3 b2 b1 b0 1 0 Symbol TA0MR to TA4MR Bit symbol TMOD0 Address 39616 to 039A16 After reset 0016 Bit name RW Function RW Operation mode select bit b1 b0 MR0 Pulse output function select bit 0 : Pulse is not output (TA iOUT pin functions as I/O port) RW 1 : Pulse is output (Note 1) (TAi OUT pin functions as a pulse output pin) MR1 External trigger select bit (Note 2) 0 : Falling edge of input signal to TAi IN pin (
M16C/6S Group Timer A 4. Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 1.12.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 1.12.10 shows TAiMR register in pulse width modulation mode. Figures 1.12.11 and 1.12.12 show examples of how a 16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates. Table 1.12.5.
M16C/6S Group Timer A Timer Ai mode register (i= 0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Symbol TA0MR to TA4MR Bit symbol TMOD0 TMOD1 Address 039616 to 039A16 After reset 0016 Bit name Operation mode select bit RW Function RW b1 b0 1 1 : PWM mode (Note 1) RW RW MR0 Must be set to “1” in PWM mode MR1 External trigger select bit (Note 2) 0: Falling edge of input signal to TAi IN pin(Note 3) RW 1: Rising edge of input signal to TAi IN pin(Note 3) MR2 Trigger select bit 0 : TAiOS bit
M16C/6S Group Timer A 1 / fi X (2 16 – 1) Count source Input signal to TA iIN pin “H” “L” Trigger is not generated by this signal 1 / fj X n PWM pulse output from TA iOUT pin “H” IR bit of TAiIC register “1” “L” “0” fj : Frequency of count source (f1, f2, f8, f32) Set to “0” upon accepting an interrupt request or by writing in program i = 0 to 4 Note 1: n = 000016 to FFFE16.
M16C/6S Group Serial I/O Serial I/O Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4. UARTi (i=0 to 2) UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.13.1 shows the block diagram of UARTi. Figure 1.13.2 shows the block diagram of the UARTi transmit/receive unit. UARTi has the following modes: • Clock synchronous serial I/O mode • Clock asynchronous serial I/O mode (UART mode).
M16C/6S Group Serial I/O 1/2 Main clock or on-chip oscillator clock f2SIO 0 f1SIO 1 PCLK1 f1SIO or f2SIO f8SIO 1/8 (UART0) 1/4 RXD polarity reversing circuit RXD0 CLK1 to CLK0 f1SIO or f2SIO 00h CKDIR Internal 01h f8SIO 10h f32SIO Receive clock Reception control circuit Clock synchronous type 001 Transmit/ receive unit TXD polarity reversing circuit TXD0 U0BRG register 0 UART transmission 010, 100, 101, 110 Clock synchronous type 001 1 / (n0+1) 1 UART reception SMD2 toSMD0 010, 100
M16C/6S Group Serial I/O IOPOL No reverse RXDi 0 RXD data reverse circuit 1 Clock synchronous type Reverse PRYE STPS PAR disabled 1SP Clock synchronous type 0 0 SP SP UART(7 bits) UARTi receive register 0 0 0 PAR 1 1 1 1 SMD2 to SMD0 UART (9 bits) PAR enabled 2SP 0 UART (7 bits) UART (8 bits) 0 0 UART 0 0 0 0 1 Clock synchronous type UART (8 bits) UART (9 bits) D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB register Logic reverse circuit + MSB/LSB conversion circuit Data
M16C/6S Group Serial I/O UARTi transmit buffer register (i=0 to 2)(Note) (b15) b7 (b8) b0 b7 Symbol U0TB U1TB U2TB b0 Address 03A316-03A216 03AB16-03AA16 037B16-037A16 After reset Indeterminate Indeterminate Indeterminate Function RW WO Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Use MOV instruction to write to this register.
M16C/6S Group Serial I/O UARTi transmit/receive mode register (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0MR to U2MR Bit symbol SMD0 Address 03A016, 03A816, 037816 After reset 0016 Function Bit name Serial I/O mode select bit (Note 2) b2 b1 b0 RW RW 0 0 0 : Serial I/O disabled 0 0 1 : Clock synchronous serial I/O mode (Note 3) 0 1 0 : I2C mode 1 0 0 : UART mode transfer data 7 bits long 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long Must not be set ex
M16C/6S Group Serial I/O UARTi transmit/receive control register 1 (i=0, 1) b7 b6 b5 b4 b3 b2 b1 Symbol U0C1, U1C1 b0 Bit symbol Address 03A516,03AD16 After reset 000000102 Function Bit name RW TE Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled RW TI Transmit buffer empty flag 0 : Data present in UiTB register 1 : No data present in UiTB register RO RE Receive enable bit 0 : Reception disabled 1 : Reception enabled RW RI Receive complete flag 0 : No data
M16C/6S Group Serial I/O UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UCON Bit symbol Address 03B016 After reset X00000002 Function Bit name UART0 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) RW UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) RW U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled
M16C/6S Group Serial I/O UARTi special mode register 2 (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address U0SMR2 to U2SMR2 036E16, 037216, 037616 Bit symbol After reset X00000002 Bit name Function RW IICM2 I 2C mode select bit 2 Refer to Table 1.16.
M16C/6S Group Serial I/O UARTi special mode register 4 (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address U0SMR4 to U2SMR4 036C16, 037016, 037416 Bit symbol Bit name After reset 0016 Function RW Start condition generate bit (Note) 0 : Clear 1 : Start RW RSTAREQ Restart condition generate bit (Note) 0 : Clear 1 : Start RW STPREQ Stop condition generate bit (Note) 0 : Clear 1 : Start RW STSPSEL SCL,SDA output select bit 0 : Start and stop conditions not output 1 : Start and stop conditions
M16C/6S Group Clock Synchronous serial I/O Mode Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.14.1 lists the specifications of the clock synchronous serial I/O mode. Table 1.14.2 lists the registers used in clock synchronous serial I/O mode and the register values set. UART2 is not available in this mode. Table 1.14.1.
M16C/6S Group Clock Synchronous serial I/O Mode Table 1.14.2.
M16C/6S Group Clock Synchronous serial I/O Mode Table 1.14.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 1.14.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 1.14.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”.
M16C/6S Group Clock Synchronous serial I/O Mode (1) Example of transmit timing (when internal clock is selected) Tc Transfer clock UiC1 register TE bit UiC1 register TI bit “1” “0” Write data to the UiTB register “1” “0” Transferred from UiTB register to UARTi transmit register “H” CTSi TCLK “L” Stopped pulsing because CTSi = “H” Stopped pulsing because the TE bit = “0” CLKi TxDi D0 D 1 D2 D3 D4 D5 D6 D7 UiC0 register TXEPT bit “1” SiTIC register IR bit “1” D 0 D 1 D 2 D3 D4 D 5 D 6 D 7
M16C/6S Group Clock Synchronous serial I/O Mode Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below.
M16C/6S Group Clock Synchronous serial I/O Mode (b) LSB First/MSB First Select Function Use the UiC0 register (i = 0 to 1)’s UFORM bit to select the transfer format. Figure 1.14.3 shows the transfer format.
M16C/6S Group Clock Synchronous serial I/O Mode (1) When the UiC1 register's UiLCH bit = 0 (no reverse) Transfer clock “H” “L” TxDi “H” (no reverse) “L” D0 D1 D2 D3 D4 D5 D6 D7 (2) When the UiC1 register's UiLCH bit = 1 (reverse) Transfer clock “H” “L” TxDi “H” (reverse) “L” D0 D1 D2 D3 D4 D5 D6 D7 Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock
M16C/6S Group Clock Synchronous serial I/O Mode _______ _______ (f) CTS/RTS Function _______ ________ When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/ ________ ________ ________ RTSi (i=0 to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H” during a transmit or receive operation, the operation stops before the next data.
M16C/6S Group UART Mode Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 1.15.1 lists the specifications of the UART mode. Table 1.15.1.
M16C/6S Group UART Mode Table 1.15.2.
M16C/6S Group UART Mode Table 1.15.3 lists the functions of the input/output pins during UART mode. Table 1.15.4 lists the P64 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.) Table 1.15.3.
M16C/6S Group UART Mode (1) Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
M16C/6S Group UART Mode • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG count source UiC1 register RE bit “1” “0” Stop bit Start bit RxDi Sampled “L” D7 D1 D0 Receive data taken in Transfer clock UiC1 register RI bit RTSi SiRIC register IR bit Reception triggered when transfer clock “1” is generated by falling edge of start bit Transferred from UARTi receive register to UiRB register “0” “H” “L” “1” “0” Cleared to “0” when interrupt request i
M16C/6S Group UART Mode Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below.
M16C/6S Group UART Mode (b) Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 1.15.4 shows serial data logic.
M16C/6S Group UART Mode _______ _______ (d) CTS/RTS Function _______ ________ ________ When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi (i=0 to 2) ________ ________ pin. Transmit operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H” during a transmit operation, the operation stops before the next data.
M16C/6S Group Special Mode Special Mode 1 (I2C mode) I2C mode is provided for use as a simplified I2C interface compatible mode. Table 1.16.1 lists the specifications of the I2C mode. Table 1.16.2 lists the registers used in the I2C mode and the register values set. Figure 1.16.1 shows the block diagram for I2C mode. Figure 1.16.2 shows SCLi timing. As shown in Table 1.16.4, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits to ‘0102’ and the IICM bit to “1”.
M16C/6S Group Special Mode Start and stop condition generation block SDAi STPSEL=1 Delay circuit SDASTSP SCLSTSP STPSEL=0 ACK=1 IICM2=1 Transmission register ACK=0 IICM=1 and IICM2=0 UARTi SDHI ACKD register DMA0 (UART0, UART2) IICM2=1 Reception register UARTi IICM=1 and IICM2=0 Start condition detection S R Q NACK D Q T Falling edge detection IICM=0 R I/O port Q STPSEL=0 IICM=1 UARTi Noise Filter UARTi receive, ACK interrupt request, DMA1 request Bus busy Stop condition detectio
M16C/6S Group Special Mode Table 1.16.2.
M16C/6S Group Special Mode Table 1.16.3.
M16C/6S Group Special Mode Table 1.16.4. I2C Mode Functions Function Clock Synchronous Serial I/O I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) Mode (SMD2 to SMD0 = 001b, IICM2 = 0 IICM2 = 1 IICM = 0) (NACK/ACK interrupt) (UART transmit/ receive interrupt) CKPH = 1 CKPH = 0 CKPH = 0 CKPH = 1 (Clock delay) (No clock delay) (Clock delay) (No clock delay) Factor of Interrupt Number 6, 7 and 10 (1, 5, 7) Start condition detection or stop condition detection (See Table 1.16.
M16C/6S Group Special Mode (1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) ACK interrupt (DMA1 request), NACK interrupt Transfer to UiRB register b15 b9 ••• b8 b7 D8 D7 b0 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 D3 D2 D1 UiRB register (2) IICM2= 0, CKPH= 1 (clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit
M16C/6S Group Special Mode • Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when the SDAi pin changes state from low to high while the SCLi pin is in the high state.
M16C/6S Group Special Mode Table 1.16.5.
M16C/6S Group Special Mode • Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 1.16.4. The UiSMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin.
M16C/6S Group Special Mode • ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is se to “1” (ACK data output), the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin. If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of the 9th bit of transmit clock pulse.
M16C/6S Group Special Mode Special Mode 2 Multiple slaves can be serially communicated from one master. Synchronous clock polarity and phase are selectable. Table 1.16.6 lists the specifications of Special Mode 2. Table 1.16.7 lists the registers used in Special Mode 2 and the register values set. Figure 1.16.5 shows communication control example for Special Mode 2. UART2 is not available in this mode. Table 1.16.6.
M16C/6S Group Special Mode P81 P80 P83 P61(CLK0) P61(CLK0) P62(RxD0) P62(RxD0) P63(TxD0) P63(TxD0) Microcomputer (Master) Microcomputer (Slave) P93 P61(CLK0) P62(RxD0) P63(TxD0) Microcomputer (Slave) Figure 1.16.5. Serial Bus Communication Control Example (UART0) R01DS0201EJ0502 Rev.5.
M16C/6S Group Special Mode Table 1.16.7.
M16C/6S Group Special Mode • Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3 register’s CKPH bit and the UiC0 register’s CKPOL bit. Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated. Figure 1.16.6 shows the transmission and reception timing in master (internal clock). Figure 1.16.
M16C/6S Group Special Mode "H" Slave control input "L" "H" Clock input (CKPOL=0, CKPH=0) "L" "H" Clock input (CKPOL=1, CKPH=0) "L" Data output timing "H" (Note) "L" Data input timing D0 D1 D2 D3 D4 D5 D6 D7 Indeterminate Figure 1.16.7.
M16C/6S Group SI/O3 and SI/O4 SI/O3 and SI/O4 SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os. Figure 1.17.1 shows the block diagram of SI/O3 and SI/O4, and Figure 1.17.2 shows the SI/O3 and SI/O4related registers. SI/O4 is derectly connected to IT800 internally. Table 1.17.1 shows the specifications of SI/O3 and SI/O4.
M16C/6S Group SI/O3 and SI/O4 S I/Oi control register (i = 3, 4) (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol S3C S4C Bit symbol SMi0 Address 036216 036616 After reset 010000016 010000016 Description Bit name Internal synchronous clock select bit SMi1 RW b1 b0 0 0 : Selecting f1SIO or f2SIO 0 1 : Selecting f8SIO 1 0 : Selecting f32SIO 1 1 : Must not be set.
M16C/6S Group SI/O3 and SI/O4 Table 1.17.1. SI/O3 and SI/O4 Specifications Item Transfer data format Transfer clock Transmission/reception start condition Interrupt request generation timing Specification • Transfer data length: 8 bits • SiC (i=3, 4) register’s SMi6 bit = “1” (internal clock) : fj/ 2(n+1) fj = f1SIO, f8SIO, f32SIO. n=Setting value of SiBRG register 0016 to FF16.
M16C/6S Group SI/O3 and SI/O4 (a) SI/Oi Operation Timing Figure 1.17.3 shows the SI/Oi operation timing 1.
M16C/6S Group SI/O3 and SI/O4 (c) Functions for Setting an SOUTi Initial Value If the SiC register’s SMi6 bit = 0 (external clock), the SOUTi pin output can be fixed high or low when not transferring. Figure 1.17.5 shows the timing chart for setting an SOUTi initial value and how to set it.
M16C/6S Group Programmable I/O Ports Programmable I/O Ports The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 55 lines P1, P4 to P9 (except P85). Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines. P85 is an input-only port and does not have a pullup resistor.
M16C/6S Group Programmable I/O Ports Direction register IT800 P40, P42, P56 Data bus Port latch Direction register P53, P54 Data bus Port latch IT800 Pull-up selection P15 Port P1 control register Data bus Port latch (Note 1) Input to respective peripheral functions Pull-up selection Direction register P60, P64, P73, P74, P76, P80, P81, P90, P92 "1" Output Data bus Port latch (Note 1) Input to respective peripheral functions Note 1: symbolizes a parasitic diode.
M16C/6S Group Programmable I/O Ports Pull-up selection Direction register P61, P65 "1" Output Data bus Port latch Switching between CMOS and Nch (Note 1) Input to respective peripheral functions Pull-up selection P83, P84 Direction register Data bus Port latch (Note 1) Input to respective peripheral functions Pull-up selection Direction register P91 Data bus Port latch (Note 1) Input to respective peripheral functions Note 1: symbolizes a parasitic diode.
M16C/6S Group Programmable I/O Ports Pull-up selection Direction register P62, P66, P71 Data bus Port latch (Note 1) Switching between CMOS and Nch Input to respective peripheral functions Pull-up selection Direction register P63, P67 “1” Data bus Port latch Output (Note 1) Switching between CMOS and Nch P85 Data bus (Note 1) Direction register P70 “1” Output Data bus Port latch (Note 2) Input to respective peripheral functions Note 1: symbolizes a parasitic diode.
M16C/6S Group Programmable I/O Ports Direction register “1” P95, P96 IT800 Output Data bus Port latch Direction register P82, P97, P41 Data bus Port latch Input to respective peripheral functions IT800 Direction register Testing signal P10, P11 Data bus Port latch Figure 1.18.4. I/O Ports (4) R01DS0201EJ0502 Rev.5.
M16C/6S Group Programmable I/O Ports (Note 2) CNVSS CNVSS signal input (Note 1) RESET RESET signal input (Note 1) Note 1: symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Note 2: A parasitic diode on the V CC side is added to the mask ROM version. Make sure the input voltage on each port will not exceed Vcc. Figure 1.18.5. I/O Pins R01DS0201EJ0502 Rev.5.
M16C/6S Group Programmable I/O Ports Port Pi direction register (i=1, 4 to 7 and 9) (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD1 PD4 to PD7 PD9 Bit symbol Address (Note 2) 03E316 03EA16, 03EB16, 03EE16, 03EF16 03F316 Bit name PDi_0 PDi_1 Port Pi0 direction bit Port Pi1 direction bit PDi_2 Port Pi2 direction bit PDi_3 Port Pi3 direction bit PDi_4 Port Pi4 direction bit PDi_5 Port Pi5 direction bit PDi_6 PDi_7 Port Pi6 direction bit Port Pi7 direction bit After reset 0016 0016 0016 Fun
M16C/6S Group Programmable I/O Ports Port Pi register (i=1, 4 to 7 and 9) b7 b6 b5 b4 b3 b2 b1 Symbol P1 P4 to P7 P9 b0 Bit symbol Address (Note 2) 03E116 03E816, 03E916, 03EC16, 03ED16 03F116 Bit name Pi_0 Port Pi0 bit Pi_1 Pi_2 Port Pi1 bit Port Pi2 bit Pi_3 Port Pi3 bit Pi_4 Port Pi4 bit Pi_5 Port Pi5 bit Pi_6 Port Pi6 bit Pi_7 Port Pi7 bit After reset Indeterminate Indeterminate Indeterminate Function RW RW RW RW RW RW RW RW RW The pin level on any I/O port which is set for
M16C/6S Group Programmable I/O Ports Pull-up control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit symbol (b2-b0) PU03 (b7-b4) Address 03FC16 After reset 0016 Bit name Function RW Nothing is assigned. When write, set to “0”. When read, its content is indeterminate. P14 to P17 pull-up 0 : Not pulled high 1 : Pulled high (Note 2) RW Nothing is assigned. When write, set to “0”. When read, its content is indeterminate.
M16C/6S Group Programmable I/O Ports Port control register b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PCR Bit symbol PCR0 Address 03FF16 Bit name Port P1 control bit After reset 0016 Function RW Operation performed when the P1 register is read 0: When the port is set for input, the input levels of P10 to P17 RW pins are read. When set for output, the port latch is read. 1: The port latch is read regardless of whether the port is set for input or output. Nothing is assigned.
M16C/6S Group Programmable I/O Ports Table 1.18.1. Unassigned Pin Handling in Single-chip Mode (Excluding Analog Pins) Pin name Connection Ports P1, P6 to P9 (excluding P8 5) After setting for input mode, connect every pin to V SS via a resistor(pull-down); or after setting for output mode, leave these pins open. (2, 3, 4) XOUT (Note 1) Open P85 Connect via resistor to V CC (pull-up) VCCA Connect to V CC VSSA Connect to V SS NOTES: 1. With external clock input to XIN pin. 2.
M16C/6S Group Programmable I/O Ports Microcomputer Port P1, P6 to P9 (except for P85) (Note 2) (Input mode) · · · (Input mode) (Output mode) ·· · Open P85 XOUT Open VCC VCCA VSSA VSS In single-chip mode Figure 1.18.10. Unassigned Pins Handling (Excluding Analog Pins) R01DS0201EJ0502 Rev.5.
M16C/6S Group Electrical Characteristics Electrical Characteristics Table 1.19.1. Absolute Maximum Ratings Condition Rated value Unit VCC Symbol Supply voltage Parameter VCC=VCCA -0.3 to 4.2 V VCCA Analog supply voltage VCC=VCCA -0.3 to 4.2 V -0.3 to VCC+0.3 V -0.3 to 6.5 V -0.3 to VCC1+0.
M16C/6S Group Electrical Characteristics Table 1.19.2. Recommended Operating Conditions (Note 1) Parameter Symbol Min. Vcc A Analog supply voltage Vss Supply voltage 0 V V Analog supply voltage 0 V VIH 3.6 Unit Supply voltage HIGH input voltage 3.3 Max. VCC Vss A 3.0 Standard Typ. VCC P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92 V 0.8VCC VCC V 0.8VCC 6.5 V 0 0.2VCC V P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92, TS -10.
M16C/6S Group Electrical Characteristics Table 1.19.3. Flash Memory Version Electrical Characteristics (Note 1) Standard Parameter Symbol Min. Typ. (Note 2) Max 100 (Note 4) Unit cycle – Erase/Write cycle (Note 3) – – Word program time (Vcc=3.3V, Topr=25°C) 75 600 µs Block erase time 8Kbyte block 0.4 9 s 16Kbyte block 0.7 9 s 32Kbyte block 1.
M16C/6S Group Electrical Characteristics Table 1.19.5. Power Supply Circuit Timing Characteristics Symbol Parameter td(P-R) Time for internal power supply stabilization during powering-on td(R-S) STOP release time td(M-L) Time for internal power supply stabilization when main clock oscillation starts Measuring condition Min. Standard Typ. Max. 2 VCC =3.0 to 3.6V Unit ms 150 s 50 s Interrupt for stop mode release CPU clock td(R-S) R01DS0201EJ0502 Rev.5.
M16C/6S Group Electrical Characteristics Table 1.19.6. Electrical Characteristics (Note) Symbol Parameter P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92, TS V OH HIGH output voltage V OH HIGH output voltage V OL LOW output voltage V OL LOW output voltage P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92, TS Hysteresis V T+-V T- V T+-V T- X OUT V I OH= -0.1mA VCC-0.5 V CC V I OL=1mA 0.5 V I OL=0.1mA 0.5 V 0.8 V 1.8 V V I =3V 4.0 A V I =0V -4.
M16C/6S Group Electrical Characteristics Table 1.19.7. Electrical Characteristics (2) (Note 1) Symbol ICC Measuring condition Parameter Power supply current (VCC=2.7 to 3.6V) In single-chip mode, the output pins are open and other pins are VSS Min. Standard Typ. Max. 95 Unit Flash memory f(BCLK)=15.36 MHz, No division 70 Flash memory Program f(BCLK)=10MHz, Vcc1=3.0V TBD mA Flash memory Erase f(BCLK)=10MHz, Vcc1=3.0V TBD mA mA Note : Referenced to VCC = 3.0 to 3.
M16C/6S Group Electrical Characteristics Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC/– 40 to 85oC/– 40 to 105oC unless otherwise specified) Table 1.19.8. External Clock Input Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time R01DS0201EJ0502 Rev.5.02 Dec 25, 2012 Standard Min. Max. Unit ns 195.
M16C/6S Group Electrical Characteristics Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC/– 40 to 85oC/– 40 to 105oC unless otherwise specified) Table 1.19.9. Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Max. Min. 150 Unit ns tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width 60 ns tw(TAL) TAiIN input LOW pulse width 60 ns Table 1.19.10.
M16C/6S Group Electrical Characteristics Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC/– 40 to 85oC/– 40 to 105oC unless otherwise specified) Table 1.19.15. Serial I/O Symbol Parameter Standard Min. Max.
M16C/6S Group Electrical Characteristics tc(TA) tw(TAH) TAi IN input tw(TAL) tc(UP) tw(UPH) TAi OUT input tw(UPL) TAi OUT input (Up/down input) During event counter mode TAi IN input (When count on falling edge is selected) th(TIN–UP) tsu(UP–TIN) TAi IN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tc(TA) TAi IN input tsu(TA IN-TA OUT) tsu(TA IN-TA OUT) tsu(TA OUT-TA IN) TAi OUT input tsu(TA OUT-TA IN) Figure 1.19.1.
M16C/6S Group Electrical Characteristics tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) th(C–D) RxDi tw(INL) INTi input tw(INH) Figure 1.19.2. Timing Diagram (2) R01DS0201EJ0502 Rev.5.
M16C/6S Group Flash Memory Version Flash Memory Version Flash Memory Performance The flash memory version has three modes—CPU rewrite, standard serial input/output, and parallel input/ output modes—in which its internal flash memory can be operated on. Note: About the parallel programmer of exclusive use, there is no schedule of development at the present time. Table 1.20.1 shows the outline performance of flash memory version (see Table 1.1.1 for the items not listed in Table 1.20.1.). Table 1.20.1.
M16C/6S Group Flash Memory Version 1. Memory Map The ROM in the flash memory version is separated between a user ROM area and a boot ROM area. Figures 1.20.1 and 1.20.2 show the block diagram of flash memory. The user ROM area is divided into several blocks, so that memory can be erased one block at a time. The user ROM area can be rewritten in all of CPU rewrite, standard serial input/output, and parallel input/output modes. The boot ROM area is reserved.
M16C/6S Group Flash Memory Version 0E800016 Block 4 : 32K bytes 0EFFFF16 0F000016 Block 3 : 32K bytes 0F7FFF16 0F800016 Block 2 : 16K bytes 0FBFFF16 0FC00016 Block 1 : 8K bytes 0FDFFF16 0FE00016 Block 0 : 8K bytes 0FFFFF16 User ROM area 0FF00016 0FFFFF16 4K bytes Boot ROM area (Reserved) Note 1: To specify a block, use an even address in that block. Note 2: Blocks 0 and 1 can be rewritten if FMR02 of FMR0 register is set to "1" (only in case of CPU rewriting mode.) Figure 1.20.2.
M16C/6S Group Flash Memory Version Boot Mode After a hardware reset which is performed by applying a high-level signal to the CNVSS and P15 pins, the microcomputer is placed in boot mode, thereby executing the program in the boot ROM area. The boot ROM area contains a standard serial input/output mode based rewrite control program which was stored in it when shipped from the factory.
M16C/6S Group Flash Memory Version ROM code protect control address b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 Symbol ROMCP Address 0FFFFF16 Bit name Bit symbol ROMCR ROMCP1 Value when shipped FF16 (Note 4) RW Function Reserved bit Set this bit to “1” RW Reserved bit Set this bit to “1” RW Reserved bit Set this bit to “1” RW Reserved bit Set this bit to “1” RW ROM code protect reset bit (Note 2, Note 4) b5 b4 ROM code protect level 1 set bit (Note 1, Note 3, Note 4) 00: Removes pr
M16C/6S Group Flash Memory Version CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board without having to use a ROM programmer, etc. Make sure the Program and the Block Erase commands are executed only on each block in the user ROM area.
M16C/6S Group Flash Memory Version • EW0 Mode The microcomputer is placed in CPU rewrite mode by setting the FMR0 register’s FMR01 bit to “1” (CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register’s FMR11 bit = 0, EW0 mode is selected. The FMR01 bit can be set to “1” by writing “0” and then “1” in succession. Use software commands to control program and erase operations.
M16C/6S Group Flash Memory Version Figure 1.21.1 shows the FMR0 and FMR1 registers. FMR00 Bit This bit indicates the operating status of the flash memory. The bit is “0” when the Program or Erase is running; otherwise, the bit is “1”. FMR01 Bit The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite mode). FMR02 Bit When FMR02 bit is “0” (rewriting is disable), block 0 and block 1 do not receive the command of a program and block erase.
M16C/6S Group Flash Memory Version Flash memory control register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address After reset FMR0 01B716 XX0000012 0 Bit name Bit symbol Function RW FMR00 RY/BY status flag 0: Busy (being written or erased) 1: Ready FMR01 CPU rewrite mode select bit (Note 1) 0: Disables CPU rewrite mode 1: Enables CPU rewrite mode RW Lock bit disable select bit (Note 2) 0: Enables lock bit 1: Disables lock bit RW Flash memory stop bit (Note 3, Note 5) 0: Enables flash mem
M16C/6S Group Flash Memory Version EW0 mode operation procedure Rewrite control program Single-chip mode Set CM0, CM1, and PM1 registers (Note1) Transfer a CPU rewrite mode based rewrite control program to any area other than the flash memory Jump to the rewrite control program which has been transferred to any area other than the flash memory (The subsequent processing is executed by the rewrite control program in any area other than the flash memory) Set the FMR01 bit by writing “0” and then “1” (C
M16C/6S Group Flash Memory Version EW1 mode operation procedure Program in ROM Single-chip mode Set CM0, CM1, and PM1 registers (Note 1) Set the FMR01 bit by writing “0” and then “1” (CPU rewrite mode enabled) Set the FMR11 bit by writing “0” and then “1” (EW1 mode) (Note 2) Execute software commands Write “0” to the FMR01 bit (CPU rewrite mode disabled) Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17 to 6 bits.
M16C/6S Group Flash Memory Version Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation Speed Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. Also, set the PM17 bit in the PM1 register to “1” (with wait state).
M16C/6S Group Flash Memory Version (6) DMA Transfer In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0 (during the auto program or auto erase period). (7) Writing Command and Data Write the command code and data at even addresses. (8) Wait Mode When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the WAIT instruction.
M16C/6S Group Flash Memory Version Software Commands Software commands are described below. The command code and data must be read and written in 16bit units, to and from even addresses in the user ROM area. When writing command code, the 8 highorder bits (D1t–D8) are ignored. Table 1.21.2.
M16C/6S Group Flash Memory Version Clear Status Register Command (5016) This command clears the status register to “0”. Write ‘xx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 in the status register will be cleared to “0”. Program Command (4016) This command writes data to the flash memory in 1 word (2 byte) units.
M16C/6S Group Flash Memory Version Block Erase Write ‘xx2016’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start. Check the FMR0 register’s FMR00 bit to see if auto erasing has finished. The FMR00 bit is “0” during auto erasing and set to “1” when auto erasing is completed.
M16C/6S Group Flash Memory Version Status Register The status register indicates the operating status of the flash memory and whether an erase or programming operation terminated normally or in error. The status of the status register can be known by reading the FMR0 register’s FMR00, FMR06, and FMR07 bits. Table 1.21.3 shows the status register.
M16C/6S Group Flash Memory Version Full Status Check When an error occurs, the FMR0 register’s FMR06 to FMR07 bits are set to “1”, indicating occurrence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check). Table 1.21.4 lists errors and FMR0 register status. Figure 1.21.6 shows a full status check flowchart and the action to be taken when each error occurs. Table 1.21.4.
M16C/6S Group Flash Memory Version Full status check FMR06 =1 and FMR07=1? YES Command sequence error (1) Execute the Clear Status Register command to clear these status flags to “0”. (2) Reexecute the command after checking that it is entered correctly. NO FMR07= 0? NO Erase error Note 1: If the error still occurs, the block in error cannot be used. YES FMR06= 0? (1) Execute the Clear Status Register command to clear the erase status flag to “0”. (2) Reexecute the Block Erase command.
M16C/6S Group Flash Memory Version Standard Serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory using the serial I/O port UART1. The serial I/O mode transfers the data serially in 8-bit units. In the standard serial I/O mode the CPU executes a control program for flash memory rewrite (using the CPU's rewrite mode), rewrite data input and so forth.
M16C/6S Group Flash Memory Version ID Code Check Function (D-version only, see Table 1.1.4 for D-version) The ID code of “ALeRASE” in ASCII code is used for forced erase function. The ID code of “Protect” in ASCII code is used for standard serial I/O mode disable function. Table 1.22.1 lists Reserved Word of ID Code. All ID code storage addresses and data must match the combinations listed in Table 1.22.1.
M16C/6S Group Flash Memory Version Forced Erase Function (D-version only, see Table 1.1.4 for D-version) Use the forced erase function in standard serial I/O mode. When the reserved word, “ALeRASE” in ASCII code, are sent from the serial programmer as ID codes, the contents of the user ROM area will be erased at once. However, if the ID codes stored in the ID code storage addresses are set to a reserved word other than “ALeRASE” (other than the combination table listed in Table 1.22.
M16C/6S Group Flash Memory Version Table 1.22.3. Functional explanation of pin (flash memory standard serial I/O mode) Pin Signal name Description I/O Apply the voltage guaranteed for Program and Erase to Vcc pin. Apply 0 V to Vss pin. VCC,VSS Power supply input CNVSS CNVSS I Connect to Vcc pin. RESET Reset input I Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock to XIN pin.
M16C/6S Group Flash Memory Version Example of Circuit Application in the Standard Serial I/O Mode Figure 1.22.1 and 1.22.2 show example of circuit application in standard serial I/O mode 1 and mode 2, respectively. Refer to the user's manual for serial programmer to handle pins controlled by a serial programmer.
M16C/6S Group Flash Memory Version Microcomputer SCLK Data output TxD Monitor output BUSY Data input RxD P15(CE) CNVss (1) In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVss input with a switch. Figure 1.22.2. Circuit Application in Standard Serial I/o Mode 2 R01DS0201EJ0502 Rev.5.
M16C/6S Group Flash Memory Version ROM Code Protect Function The ROM code protect function inhibits the flash memory from being read or rewritten. (Refer to the description of the functions to inhibit rewriting flash memory version.) R01DS0201EJ0502 Rev.5.
M16C/6S Group IT800AFE (Analog Front End) IT800AFE (Analog Front End) 1. The block diagram of analog front end Analog front end (AFE) part is the circuit located between M16C/6S and a power line, and M16C/6S build in DAC, preamplifier, and ADC. There are the following two signal circuits in AFE.
M16C/6S Group IT800AFE (Analog Front End) About DAC (Digital to Analog Converter) DAC of built-in in M16C/6S is current output type 10 bit DAC. The standard level of output current can be set up by the external resistance linked to a built-in standard power supply. A DAC circuit and a load circuit are shown in Figure 1.23.2. The typical characteristic is shown in Table 1.23.1. 10 bit DAC Iout DATA Vref D9-D0 10 7 Matrix Current Cell Rout 2.1k(1%) Cout 33pF Line Driver Amp + - 6 Ioutc Routc 2.
M16C/6S Group IT800AFE (Analog Front End) In the circumference of a DAC circuit, it is cautious of the following point and a constant is set up. (a)Full-scale output current of DAC Although the current by which DAC is outputted to a pin (Iout/Ioutc) according to the change width of an internal bit changes, total is fixed and serves as full-scale output current (IFULL). This IFULL can be set up by the following formula.
M16C/6S Group IT800AFE (Analog Front End) (2)Receiving circuit (a)Preamplifier A preamplifier circuit consists of two CMOS operational amplifiers as shown in Figure 1.23.3, the first opamp is connected as gain stage with gain of 20dB and the second opamp is connected as a voltage follower for driving of external filter. 3.3V 10k Vref 10k 0.1 F M16C/6S Pre-InP Input filter Amplifier Pre_BOut Buffer Pre-InN Figure 1.23.3 Consists of Preamp circuit Table 1.23.
M16C/6S Group IT800AFE (Analog Front End) (b)ADC (Analog to Digital Converter) The output of the channel filter (maximum of three) connected outside is connected to 1 bit ADC which consists of an operational amplifier and a comparator. M16C/6S build in ADC of three equivalent performances. The circuit of one ADC has composition shown in the following figure. R1/R2/R3 C1/C2/C3 AMP1_Out/AMP2_Out/ AMP3_Out Channel Filter CH1_InP/CH2_InP/ CH3_InP 0.22 F 1k AMP1_IN/ AMP2_IN/ AMP3_IN/ Vref 3.
M16C/6S Group Usage Notes Usage Notes Register Setting Immediate values should be set in the registers containing write-only bits. When establishing a new value by modifying a previous value, write the previous value into RAM as well as the register. Change the contents of the RAM and then transfer the new value to the register. R01DS0201EJ0502 Rev.5.
M16C/6S Group Usage Notes Power Control When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not excute any instructions which can generate a write to RAM between the JMP.B and WAIT instructions. Disable the DMA transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT instruction, insert at least 4 NOP instructions.
M16C/6S Group Usage Notes Changing the Interrupt Generate Factor If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt requested). If you changed the interrupt generate factor for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to 0 (interrupt not requested).
M16C/6S Group Usage Notes Watchdog Timer Interrupt Initialize the watchdog timer after the watchdog timer interrupt occurs. DMAC Write to DMAE Bit in DMiCON Register (i = 0 to 1) When both of the conditions below are met, follow the steps below. (a) Conditions • The DMAE bit is set to 1 again while it remains set (DMAi is in an active state). • A DMA request may occur simultaneously when the DMAE bit is being written.
M16C/6S Group Usage Notes Timers Timer A Timer A (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to 1 (count starts). Always make sure the TAiMR register is modified while the TAiS bit remains 0 (count stops) regardless whether after reset or not.
M16C/6S Group Usage Notes Timer A (One-shot Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).
M16C/6S Group Usage Notes Timer A (Pulse Width Modulation Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using bits TA0TGL and TA0TGH in the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).
M16C/6S Group Usage Notes Serial I/O Clock-Synchronous Serial I/O Transmission/reception With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side that the reception has become ready. The output level of the RTSi pin goes to “H” when reception starts.
M16C/6S Group Usage Notes UART Mode Special Mode 1 (I2C bus Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to 0 and wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ, RSTAREQ and STPREQ) from 0 to 1.
M16C/6S Group Usage Notes Flash Memory Version Functions to Inhibit Rewriting Flash Memory Rewrite ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode. The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash memory cannot be read or written in parallel I/O mode.
M16C/6S Group APPENDIX APPENDIX IT800DLL Explanatory Note June 2, 2005 IT800 Data Link Layer – Functionality and Advantages 1. Scope This document describes the functionality of the Data Link Layer (DLL) implemented in the products based on Yitran's IT800 technology for narrowband networking using the power line wiring.
M16C/6S Group APPENDIX IT800DLL Explanatory Note June 2, 2005 3. IT800DLL Main functions The DLL main functions and mechanisms are described in the following table: Function Carrier sense Channel access prioritization Description Provides the carrier detection (CD) signal for triggering the media access algorithms as a function of the PHY correlator output, which indicates the probability of a signal on the line.
M16C/6S Group APPENDIX IT800DLL Explanatory Note June 2, 2005 4. Other DLL implementations In case of using other implementations of the DLL or considering such implementations, please be advised to consider the following issues: 1. Co-existence: Implementing a different channel access scheme, prioritization levels, packet formats and so forth, will not allow your product to co-exist with other IT800 based products that may share the same medium.
REVISION HISTORY Rev. M16C/6S Group Date Description Summary Page 1.00 Jun 25, 2003 - 2.00 Aug 18, 2003 P1 P2 P3 P4 P5 P7 P8 P9 P12 P14 P15 P20 P24 P25 P26 P27 P29 P30 P33 P36 P37 P42 P43 P45 P52 P54 P62 P83 P84 P85 P88 P90 P92 P94 P95 P100 P107 P119 First edition issued L7 is changed. T1.1.1 is changed. F1.1.1 is changed. T1.1.2 is changed. F1.1.2 is changed. T1.1.3 is changed. T1.1.4 is changed. L5 and F1.2.1 are changed. Table of register is changed. Table of register is changed.
Rev. Date Description Summary Page 2.00 Aug 18, 2003 P121 PT1.16.4 is changed. P127 T1.16.6 is changed. P128 F1.16.5 is changed. – Special Mode 3 is deleted. P139 L10 to L11 and L17 to L19 and L21 and L30 to L32 and L38 to L40 are changed. P140 F1.18.1 is changed. P141 F1.18.2 is changed. P143 F1.18.4 is changed. P147 F1.18.8 is changed. P149 T1.18.1 is changed. P151 T1.19.1 is changed. P152 T1.19.2 is changed. P153 T1.19.4 is changed. P154 T1.19.5 is changed. P155 T1.19.
Rev. Date Description Summary Page 2.01 Oct 27, 2003 P3 P7 P22 P23 P141 P143 P144 P178 3.00 Jul 22, 2004 P1 P2 P4 P5 P6 P7 P9 P22 P23 P26 P27 P32 P33 P36 P37 P38 P44 P45 P46 P48 P49 P55 P58 P59 Between P60 to P61 P63 P79 P137 P140 P147 P148 P149 P150 P151 P152 L1 to L2 are changed. F1.1.1 is changed. T1.1.3 is changed. L3 to L4 are changed. (3) Setting PLC Mode is changed. T1.6.4 and F1.6.1 and F1.6.2 are changed. F1.18.4 is changed. F1.18.6 is changed. F1.18.7 is changed.
Rev. Date Description Summary Page 3.00 Jul 22, 2004 3.01 Feb 17, 2005 4.00 Aug 05, 2005 P153 T.1.19.6 is changed. Deletion of a voltage display of a header. P154 T.1.19.7 is changed. Deletion of a voltage display of a header. 155 Deletion of a voltage display of a header. P156 Deletion of a voltage display of a header. P157 T.1.19.15 is changed. P163 T.1.20.3 is changed. P167 T.1.21.2 is changed. P168 T.1.21.3 is changed. P169 T.1.21.4 is changed. P170 Text is changed.
Rev. Date Description Summary Page 4.00 Aug 05, 2005 P110 T.1.15.2 is changed. P114 L1-L11 are added. P116 L1-L10 are added. P118 F.1.16.1 is changed. P119 T.1.16.2 is changed. P121 T.1.16.4 is changed. P123 L8-L16 are added. P130 Text is changed. P137 L2, L5-L6 and L12 are changed. P147 Note is added. P151 T.1.19.3 is changed. P160 T.1.20.1 is changed. P165 L12-L13 are added. P176 T.1.21.4 is changed. P188 to Appendix is added. P190 5.
Rev. Date Description Summary Page 5.00 Apr 24, 2009 92 “UARTi (i=0 to 2)” is revised. 117 Table 1.16.1 “Error detection” is revised. 147 Table 1.18.1 title “(Excluding Analog Pins)” is added. 148 Figure 1.18.10 title “(Excluding Analog Pins)” is added. 149 Table 1.19.1 Topr is revised, Note 1 is revised. 150 Table 1.19.2 “VCC1” → “VCC” , Note 1 is revised. 152 Table 1.19.5 Note is deleted. 153 Table 1.19.6 Note is revised. 154 Table 1.19.7 Standard “95” is added. Note is revised.
Rev. Date Description Summary Page 5.02 Dec 25, 2012 180, 181 ID Code Check Function, Forced Erase Function, Standard Serial I/O Mode Disable Function are added All trademarks and registered trademarks are the property of their respective owners.
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.