Datasheet

Rev.2.10 Aug 25, 2006 page 51 of 67
REJ03B0061-0210
M16C/6N Group (M16C/6NL, M16C/6NN) 5. Electric Characteristics
Under development
This document is under development and its contents are subject to change.
Figure 5.10 Timing Diagram (8)
Read timing
Write timing
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
ALE
RD
ADi
/DBi
ADi
BHE
BCLK
CSi
ALE
ADi
/DBi
tcyc
t d(BCLK-AD)
25ns.max
tcyc
Data output
t h(BCLK-CS)
4ns.min
t d(BCLK-CS)
25ns.max
t d(BCLK-ALE)
25ns.max
t h(BCLK-ALE)
-4ns.min
t d(BCLK-RD)
25ns.max
t h(BCLK-RD)
0ns.min
t SU(DB-RD)
40ns.min
t h(RD-DB)
0ns.min
t h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
t h(BCLK-AD)
4ns.min
t d(BCLK-CS)
25ns.max
t d(BCLK-AD)
25ns.max
t h(BCLK-DB)
4ns.min
t h(BCLK-WR)
0ns.min
t h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t h(BCLK-AD)
4ns.min
t h(BCLK-CS)
4ns.min
t d(BCLK-ALE)
25ns.max
t d(BCLK-WR)
25ns.max
t
-4ns.min
t h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
Data input
Address
Address
ADi
BHE
WR, WRL
WRH
t d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
t d(AD-RD)
0ns.min
t dZ(RD-AD)
8ns.max
t ac3(RD-DB)
t d(BCLK-DB)
40ns.max
(0.5 ✕ tcyc-10)ns.min
t h(WR-CS)
t d(AD-WR)
0ns.min
t h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
t d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
(2.5 ✕ tcyc-45)ns.max
(no multiplex)
(no multiplex)
tcyc =
1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
IL = 0.8 V, V IH = 2.0 V
Output timing voltage : V
OL = 0.4 V, V OH = 2.4 V
td(DB-WR)
(2.5 ✕ tcyc-40)ns.min
h(BCLK-ALE)
(0.5 ✕ tcyc-15)ns.min
th(ALE-AD)
VCC = 5 V