User`s manual

Chapter 5. Specifications
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Vcc=5V
(3) Timing Requirements
Tables 5.4 and Figure 5.3 list the timing requirements.
Table 5.4 Timing requirements
Actual MCU [ns] This product [ns]
Symbol Item
Min. Max. Min. Max.
tsu(DB-RD) Data input setup time 40 55
tsu(RDY-BCLK) RDY* input setup time 30 45
tsu(HOLD-BCLK) HOLD* input setup time 40 55
th(RD-DB) Data input hold time 0 See left
th(BCLK-RDY) RDY* input hold time 0 See left
th(BCLK-HOLD) HOLD* input hold time 0 See left
td(BCLK-HLDA) HLDA* output delay time 40 See left
Figure 5.3 Timing requirements
* Compared with an actual MCU, this product enters high-impedance state after a 0.5 cycle delay.
Common to "with wait" and "no-wait" (actual MCU)
Common to "with wait" and "no-wait" (this product)
tsu(HOLD-BCLK)
td(BCLK-HLDA)
td(BCLK-HLDA)
th(BCLK-HOLD)
tsu(HOLD-BCLK)
td(BCLK-HLDA)
td(BCLK-HLDA)
th(BCLK-HOLD)
BCLK
HOLD input
HLDA output
P0,P1,P2,P3,P4,
P5
0 –P5 2
Hi-Z
BCLK
HOLD input
HLDA output
P0,P1,P2,P3,P4,
P5
0 –P5 2
Hi-Z