User`s manual

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Vcc=5V
Figure 5.1 Memory expansion mode and microprocessor mode (3-wait, accessing external area)
Read
Write
BCLK
CSi
ADi
BHE
ALE
RD
DBi
td(BCLK-CS)
th(BCLK-CS)
tcyc
td(BCLK-AD)
th(BCLK-AD)
th(RD-CS)
td(BCLK-ALE)
th(BCLK-ALE)
th(RD-AD)
td(BCLK-RD)
th(BCLK-RD)
tac2(RD-DB)
Hi-Z
tsu(DB-RD)
th(RD-DB)
BCLK
CSi
ADi
BHE
ALE
WR,
WRL,WRH
DBi
td(BCLK-CS)
th(BCLK-CS)
tcyc
td(BCLK-AD)
td(BCLK-ALE)
th(BCLK-ALE)
th(WR-AD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
Hi-Z
td(DB-WR)
th(BCLK-AD)
th(WR-CS)
th(WR-DB)
th(BCLK-DB)