Datasheet

Rev.2.40 Aug 25, 2006 page 70 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.18 Timing Diagram (6)
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
t d(BCLK-CS)
25ns.max
t d(BCLK-AD)
25ns.max
t d(BCLK-ALE)
25ns.max
t h(BCLK-ALE)
-4ns.min
t d(BCLK-RD)
25ns.max
Hi-Z
t SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
t h(BCLK-RD)
0ns.min
t h(RD-AD)
0ns.min
t h(BCLK-AD)
4ns.min
t h(BCLK-CS)
4ns.min
tcyc
Hi-Z
t d(BCLK-CS)
25ns.max
t d(BCLK-AD)
25ns.max
t d(BCLK-ALE)
25ns.max
t h(BCLK-ALE)
-4ns.min
t d(BCLK-WR)
25ns.max
t h(BCLK-CS)
4ns.min
t h(BCLK-AD)
4ns.min
t h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t h(BCLK-WR)
0ns.min
t d(BCLK-DB)
40ns.max
t d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
t h(BCLK-DB)
4ns.min
t h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t ac2(RD-DB)
(3.5 ✕ tcyc-45)ns.max
tcyc =
1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
IL = 0.8 V, VIH = 2.0 V
Output timing voltage : V
OL = 0.4 V, VOH = 2.4 V
VCC = 5 V