Datasheet

Rev.2.40 Aug 25, 2006 page 47 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.6 Timing Diagram (4)
BCLK
CSi
t d(BCLK-CS)
25ns.max
ADi
t d(BCLK-AD)
25ns.max
ALE
25ns.max
t h(BCLK-ALE)
-4ns.min
RD
25ns.max
t h(BCLK-RD)
0ns.min
t h(BCLK-AD)
4ns.min
t h(BCLK-CS)
4ns.min
Hi-Z
DBi
t SU(DB-RD)
40ns.min
t h(RD-DB)
0ns.min
tcyc
BHE
Read timing
WR,WRL,
WRH
25ns.max
t h(BCLK-WR)
0ns.min
BCLK
CSi
t d(BCLK-CS)
25ns.max
ADi
t d(BCLK-AD)
25ns.max
ALE
25ns.max
t d(BCLK-ALE)
t h(BCLK-ALE)
-4ns.min
t h(BCLK-AD)
4ns.min
t h(BCLK-CS)
4ns.min
tcyc
t h(WR-AD)
BHE
t d(BCLK-DB)
40ns.max
4ns.min
t h(BCLK-DB)
t d(DB-WR)
(0.5 ✕ tcyc-40)ns.min
(0.5 ✕ tcyc-10)ns.min
t h(WR-DB)
DBi
Write timing
t d(BCLK-ALE)
t d(BCLK-RD)
t d(BCLK-WR)
0ns.min
t h(RD-AD)
t ac2(RD-DB)
Hi-Z
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
(1.5 ✕ tcyc-45)ns.max
tcyc =
1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
IL = 0.8 V, VIH = 2.0 V
Output timing voltage : V
OL = 0.4 V, VOH = 2.4 V
(0.5 ✕ tcyc-10)ns.min
VCC = 5 V