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Under development This document is under development and its contents are subject to change M16C/6N Group (M16C/6N4) Renesas MCU REJ03B0003-0240 Rev.2.40 Aug 25, 2006 1. Overview The M16C/6N Group (M16C/6N4) of MCUs are built using the high-performance silicon gate CMOS process using the M16C/60 Series CPU core and are packaged in 100-pin plastic molded QFP and LQFP. These MCUs operate using sophisticated instructions featuring a high level of instruction efficiency.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1. Overview 1.2 Performance Overview Table 1.1 lists the Functions and Specifications for M16C/6N Group (M16C/6N4). Table 1.1 Functions and Specifications for M16C/6N Group (M16C/6N4) Specification Item Normal-ver. T/V-ver. CPU Number of fundamental 91 instructions instructions Minimum instruction 41.7 ns (f(BCLK) = 24 MHz, 50.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1. Overview 1.3 Block Diagram Figure 1.1 shows a Block Diagram. 8 Port P0 8 8 Port P1 Port P3 Three-phase motor control circuit CRC calculation circuit (CCITT) (Polynomial: X16+X12+X5+1) Watchdog timer (15 bits) Rev.2.40 Aug 25, 2006 REJ03B0003-0240 page 3 of 88 ISP RAM (2) INTB PC FLG Multiplier 8 Figure 1.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1. Overview 1.4 Product Information Table 1.2 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages. Table 1.2 Product Information As of Aug. 2006 Type No. ROM Capacity RAM Capacity Package Type (2) Remarks M306N4FCFP 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A Flash Normal-ver.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1. Overview 1.
Under development This document is under development and its contents are subject to change. 1.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1. Overview Table 1.3 List of Pin Names (1) Pin No.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1. Overview Table 1.4 List of Pin Names (2) Pin No.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1. Overview 1.6 Pin Functions Tables 1.5 to 1.7 list the Pin Functions. Table 1.5 Pin Functions (1) Signal Name Power supply input Pin Name VCC1, VCC2, VSS I/O Type Description I Apply 4.2 to 5.5 V (T/V-ver.), 3.0 to 5.5 V (Normal-ver.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1. Overview Table 1.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 1. Overview Table 1.7 Pin Functions (3) Signal Name I/O port Pin Name P0_0 to P0_7 I/O Type Description 8-bit I/O ports in CMOS, having a direction register to select I/O P1_0 to P1_7 an input or output. P2_0 to P2_7 Each pin is set as an input port or output port.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two register banks.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 2. Central Processing Unit (CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 3. Memory 3. Memory Figure 3.1 shows a Memory Map. The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 128-Kbyte internal ROM is allocated to the addresses from E0000h to FFFFFh. As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) An SFR (Special Function Register) is a control register for a peripheral function. Tables 4.1 to 4.16 list the SFR Information. Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs) Table 4.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) 5. Electrical Characteristics 5.1 Electrical Characteristics (T/V-ver.) Table 5.1 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit VCC Supply voltage (VCC1 = VCC2) VCC = AVCC –0.3 to 6.5 V AVCC Analog supply voltage VCC = AVCC –0.3 to 6.5 V –0.3 to VCC+0.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Table 5.2 Recommended Operating Conditions (1) Symbol (1) Parameter Min. Standard Max. Typ. Unit VCC Supply voltage (VCC1 = VCC2) AVCC Analog supply voltage VCC V VSS Supply voltage 0 V AVSS Analog supply voltage 0 V VIH HIGH input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, 0.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Table 5.3 Recommended Operating Conditions (2) Symbol f(XIN) (1) Parameter Min. Main clock input oscillation No wait Mask ROM version VCC = 4.2 to 5.5 V frequency (2) (3) (4) Standard Max. Typ.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Table 5.4 Electrical Characteristics (1) Parameter Symbol (1) Measuring Condition Standard Min. Typ. Max. VCC VCC-2.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.5 Electrical Characteristics (2) Symbol ICC 5. Electric Characteristics (T/V-ver.) (1) Parameter Power supply Measuring Condition In single-chip mode, Mask ROM current Min. f(BCLK) = 20 MHz, Standard Typ. Max. 18 32 Unit mA PLL operation, the output pins are (VCC = 4.2 to 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) (1) Table 5.6 A/D Conversion Characteristics Symbol Parameter – Resolution INL Integral 10 bits Min. VREF = VCC VREF ANEX0, ANEX1 input, AN0 to AN7 input, Standard Typ. Max.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Table 5.8 Power Supply Circuit Timing Characteristics Symbol Measuring Condition Parameter Min. Standard Typ. Max. 2 Unit td(P-R) Time for internal power supply stabilization during powering-on VCC = 4.2 to 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 5.11 Timer A Input (Counter Input in Event Counter Mode) Parameter Symbol tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) =5V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) =5V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) =5V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 25ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 ✕ tcyc-45)ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 0ns.min -4ns.min 25ns.max ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 25ns.max RD tac2(RD-DB) (1.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(RD-AD) th(BCLK-ALE) -4ns.min 0ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 25ns.max RD tac2(RD-DB) (2.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) VCC = 5 V Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) td(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) 0ns.min th(BCLK-ALE) 25ns.max -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 25ns.max 0ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) VCC = 5 V Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BCLK-CS) th(RD-CS) (0.5 ✕ tcyc-10)ns.min tcyc 25ns.max th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 ✕ tcyc-25)ns.min ADi /DBi th(ALE-AD) (0.5 ✕ tcyc-15)ns.min Address 8ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.) VCC = 5 V Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK th(RD-CS) (0.5 ✕ tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 4ns.min 25ns.max CSi td(AD-ALE) (0.5 ✕ tcyc-25)ns.min ADi /DBi th(ALE-AD) (0.5 ✕ tcyc-15)ns.min Address td(BCLK-AD) td(AD-RD) 25ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) 5.2 Electrical Characteristics (Normal-ver.) Table 5.26 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit VCC Supply voltage (VCC1 = VCC2) VCC = AVCC –0.3 to 6.5 V AVCC Analog supply voltage VCC = AVCC –0.3 to 6.5 V –0.3 to VCC+0.3 V –0.3 to 6.5 V –0.3 to VCC+0.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Table 5.27 Recommended Operating Conditions (1) Symbol (1) Parameter Min. Standard Max. Typ. Unit VCC Supply voltage (VCC1 = VCC2) AVCC Analog supply voltage VCC V VSS Supply voltage 0 V AVSS Analog supply voltage 0 V VIH HIGH input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, 0.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Table 5.28 Recommended Operating Conditions (2) Symbol f(XIN) (1) Parameter Min. Main clock input oscillation No wait Mask ROM version VCC = 3.0 to 5.5 V frequency (2) (3) (4) Standard Max. Typ.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Table 5.29 A/D Conversion Characteristics Symbol Parameter – Resolution INL Integral 10 bits Measuring Condition Min. VREF = VCC VREF ANEX0, ANEX1 input, AN0 to AN7 input, Standard Typ. Max.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Table 5.31 Power Supply Circuit Timing Characteristics Symbol Measuring Condition Parameter Min. Standard Typ. Max. 2 Unit td(P-R) Time for internal power supply stabilization during powering-on VCC = 3.0 to 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Table 5.32 Electrical Characteristics (1) Symbol VOH HIGH output voltage VOH HIGH output voltage VOH HIGH output voltage HIGH output voltage VOL LOW output voltage VOL LOW output voltage VOL LOW output voltage LOW output voltage VT+-VT- Hysteresis (1) VCC = 5 V Standard Parameter Measuring Condition Min. Typ. Max.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Table 5.33 Electrical Characteristics (2) Symbol ICC 5. Electric Characteristics (Normal-ver.) (1) Parameter Power supply Measuring Condition In single-chip mode, Mask ROM current Min. f(BCLK) = 24 MHz, Standard Typ. Max. 20 36 Unit mA PLL operation, the output pins are (VCC = 3.0 to 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 5.36 Timer A Input (Counter Input in Event Counter Mode) Parameter Symbol tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) =5V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) =5V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) =5V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 25ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 ✕ tcyc-45)ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 0ns.min -4ns.min 25ns.max ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 25ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(RD-AD) th(BCLK-ALE) -4ns.min 0ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 25ns.max RD tac2(RD-DB) (2.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) VCC = 5 V Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) td(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) 0ns.min th(BCLK-ALE) 25ns.max -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 25ns.max 0ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) VCC = 5 V Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BCLK-CS) th(RD-CS) (0.5 ✕ tcyc-10)ns.min tcyc 25ns.max th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 ✕ tcyc-25)ns.min ADi /DBi th(ALE-AD) (0.5 ✕ tcyc-15)ns.min Address 8ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) VCC = 5 V Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK th(RD-CS) (0.5 ✕ tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 4ns.min 25ns.max CSi td(AD-ALE) (0.5 ✕ tcyc-25)ns.min ADi /DBi th(ALE-AD) (0.5 ✕ tcyc-15)ns.min Address td(BCLK-AD) td(AD-RD) 25ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Table 5.51 Electrical Characteristics Symbol VOH HIGH output voltage (1) VCC = 3.3 V Standard Parameter Measuring Condition Min. Typ. Max. P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –1 mA VCC VCC-0.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) = 3.3 V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) = 3.3 V Table 5.54 Timer A Input (Counter Input in Event Counter Mode) Parameter Symbol tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) = 3.3 V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) = 3.3 V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) = 3.3 V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) = 3.3 V Table 5.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) VCC = 3.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 30ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 ✕ tcyc-60)ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 0ns.min -4ns.min 30ns.max ALE td(BCLK-RD) th(BCLK-RD) 30ns.max 0ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 30ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 30ns.max ADi BHE td(BCLK-ALE) 30ns.max th(RD-AD) th(BCLK-ALE) -4ns.min 0ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 30ns.max RD tac2(RD-DB) (2.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.3 V (For 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 30ns.max CSi th(BCLK-AD) td(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) 0ns.min th(BCLK-ALE) 30ns.max -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 30ns.max 0ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) VCC = 3.3 V Memory Expansion Mode and Microprocessor Mode (For 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BCLK-CS) th(RD-CS) (0.5 ✕ tcyc-10)ns.min tcyc 40ns.max th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 ✕ tcyc-40)ns.min ADi /DBi Address th(ALE-AD) (0.5 ✕ tcyc-15)ns.min 8ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.3 V (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK th(RD-CS) (0.5 ✕ tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 6ns.min 40ns.max CSi td(AD-ALE) (0.5 ✕ tcyc-40)ns.min ADi /DBi th(ALE-AD) (0.5 ✕ tcyc-15)ns.
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N4) Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JB-A Previous Code 100P6S-A MASS[Typ.] 1.6g HD *1 D 80 51 81 50 E *2 HE NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
REVISION HISTORY Rev. Date M16C/6N Group (M16C/6N4) Data Sheet Description Page Summary 1.00 Jun. 30, 2003 – First edition issued 2.00 Nov. 10, 2004 – Revised edition issued 1 2 4 5 6 8 12 13 19 27 28 29 31 32 * Words standardizes (on-chip oscillator) * 100P6Q-A (100-pin version) is added. * Revised parts and revised contents are as follows (except for change of a layout and an expressional change). 1. Overview 3rd line: "and LQFP" is added. Table 1.
REVISION HISTORY Rev. Date 2.00 Nov. 10, 2004 M16C/6N Group (M16C/6N4) Data Sheet Description Page Summary 34 Table 5.6 A/D Conversion Characteristics: "Tolerance Level Impedance" is added. 35 Table 5.8 Power Supply Circuit Timing Characteristics: "td(M-L)" is deleted. 36 Table 5.10 Memory Expansion Mode and Microprocessor Mode: "td(BCLK-HLDA)" is deleted. Figure 5.2 Power Supply Circuit Timing Diagram is added. 38 Table 5.21 Serial I/O: Min.
REVISION HISTORY Rev. Date 2.40 Aug. 25, 2006 M16C/6N Group (M16C/6N4) Data Sheet Description Page 7, 8 Summary Tables 1.3 and 1.4 List of Pin Names (1)(2) are added. 9 Table 1.5 Pin Functions (1) 22 Table 4.8 SFR Information (8) • 3.0 to 5.5 V (Normal-ver.) is added to Description of Power supply input. • The value of After Reset in IDB0 register is revised. • The value of After Reset in IDB1 register is revised. 33 Table 5.3 Recommended Operating Conditions (2) • Power supply ripple is deleted.
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