Datasheet

M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 19 of 96
REJ03B0001-0241
Figure 1.8 Pin Configuration (Top View)
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P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
P1_0/D8
P1_1/D9
P1_2/D10
P1_3/D11 P1_4/D12
VREF
AVSS
VCC1
XIN
XOUT
VSS
RESET
CNVSS
P8_7/XCIN
P8_6/XCOUT
BYTE
P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) P3_0/A8(/-/D7) P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17
P4_2/A18
P4_3/A19
P7_4/TA2OUT/W
P7_6/TA3OUT
P5_6/ALE
P7_7/TA3IN
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
VCC2 VSS
P5_7/RDY/CLKOUT
P4_5/CS1
P4_6/CS2
P4_7/CS3
AVCC
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P10_0/AN0
P10_1/AN1
P10_2/AN2
P10_3/AN3
P9_3/DA0/TB3IN P9_4/DA1/TB4IN
P9_5/ANEX0/CLK4
P9_6/ANEX1/SOUT4
P9_1/TB1IN/SIN3
P9_2/TB2IN/SOUT3
P8_0/TA4OUT/U
P6_0/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P8_2/INT0 P8_3/INT1
P8_5/NMI
P9_7/ADTRG/SIN4
P4_4/CS0
P5_0/WRL/WR
P5_1/WRH/BHE
P9_0/TB0IN/CLK3
P8_4/INT2/ZP
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/TA0IN/TB5IN
(1)
P7_0/TXD2/SDA2/TA0OUT
(1)
P7_5/TA2IN/W
P7_3/CTS2/RTS2/TA1IN/V
P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P8_1/TA4IN/U
<VCC2>
(2)
<VCC1>
(2)
Package : PLQP0100KB-A (100P6Q-A)
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
PIN CONFIGURATION (top view)
M16C/62P Group
(M16C/62P, M16C/62PT)