Datasheet

M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics
Rev.2.41 Jan 10, 2006 Page 59 of 96
REJ03B0001-0241
Figure 5.6 Timing Diagram (4)
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
25ns.max
ALE
25ns.max
-4ns.min
RD
25ns.max
th(BCLK-RD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
Hi-Z
DBi
th(RD-DB)
0ns.min
0ns.min
th(RD-AD)
BHE
tcyc
Read timing
td(BCLK-AD)
td(BCLK-ALE)
th(BCLK-ALE)
tsu(DB-RD)
td(BCLK-RD)
40ns.min
tac1(RD-DB)
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Measuring conditions
· V
CC1=VCC2=5V
· Input timing voltage : V
IL=0.8V, VIH=2.0V
· Output timing voltage : V
OL=0.4V, VOH=2.4V
WR, WRL,
WRH
25ns.max
th(BCLK-WR)
0ns.min
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
25ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(WR-AD)
BHE
td(BCLK-DB)
40ns.max
4ns.min
th(BCLK-DB)
td(DB-WR)
(0.5 × t
cyc-40)ns.min
th(WR-DB)
DBi
Write timing
td(BCLK-WR)
Hi-Z
(0.5 × tcyc-45)ns.max
tcyc=
1
f(BCLK)
(0.5 × tcyc-10)ns.min
(0.5 × tcyc-10)ns.min
VCC1=VCC2=5V