Datasheet

M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics
Rev.2.41 Jan 10, 2006 Page 81 of 96
REJ03B0001-0241
Figure 5.21 Timing Diagram (9)
Read timing
Write timing
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
BCLK
CSi
ALE
RD
ADi
/DBi
ADi
BHE
(No multiplex)
BCLK
CSi
ALE
ADi
/DBi
tcyc
td(BCLK-AD)
40ns.max
tcyc
Data output
th(BCLK-CS)
6ns.min
td(BCLK-CS)
40ns.max
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
td(BCLK-RD)
40ns.max
th(BCLK-RD)
0ns.min
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
th(RD-AD)
(0.5×t
cyc-10)ns.min
th(BCLK-AD)
4ns.min
td(BCLK-CS)
40ns.max
td(BCLK-AD)
40ns.max
th(BCLK-DB)
4ns.min
th(BCLK-WR)
0ns.min
th(WR-AD)
(0.5×t
cyc-10)ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
td(BCLK-ALE)
40ns.max
td(BCLK-WR)
40ns.max
th(WR-DB)
(0.5×t
cyc-10)ns.min
Data input
Address
Address
ADi
BHE
(No multiplex)
WR, WRL
WRH
th(ALE-AD)
td(AD-ALE)
(0.5×tcyc-40)ns.min
td(AD-RD)
0ns.min
tdZ(RD-AD)
8ns.max
tac3(RD-DB)
td(BCLK-DB)
50ns.max
(0.5×tcyc-10)ns.min
th(WR-CS)
td(DB-WR)
(2.5×tcyc-50)ns.min
td(AD-WR)
0ns.min
th(RD-CS)
(0.5×tcyc-10)ns.min
td(AD-ALE)
(0.5×tcyc-40)ns.min
(2.5×tcyc-60)ns.max
tcyc=
1
f(BCLK)
th(BCLK-ALE)
-4ns.min
(0.5×tcyc-15)ns.min
VCC1=VCC2=3V
Measuring conditions
· V
CC1=VCC2=3V
· Input timing voltage : V
IL=0.6V, VIH=2.4V
· Output timing voltage : V
OL=1.5V, VOH=1.5V