Datasheet

M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics
Rev.2.41 Jan 10, 2006 Page 78 of 96
REJ03B0001-0241
Figure 5.18 Timing Diagram (6)
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
td(BCLK-CS)
30ns.max
td(BCLK-AD)
30ns.max
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
td(BCLK-RD)
30ns.max
Hi-Z
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
th(BCLK-RD)
0ns.min
th(RD-AD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
Hi-Z
td(BCLK-CS)
30ns.max
td(BCLK-AD)
30ns.max
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
td(BCLK-WR)
30ns.max
th(BCLK-CS)
4ns.min
th(BCLK-AD)
4ns.min
th(WR-AD)
(0.5 × t
cyc-10)ns.min
th(BCLK-WR)
0ns.min
td(BCLK-DB)
40ns.max
td(DB-WR)
(1.5 × t
cyc-40)ns.min
th(BCLK-DB)
4ns.min
th(WR-DB)
(0.5 × t
cyc-10)ns.min
tac2(RD-DB)
(2.5 × tcyc-60)ns.max
tcyc=
1
f(BCLK)
VCC1=VCC2=3V
Measuring conditions
· V
CC1=VCC2=3V
· Input timing voltage : V
IL=0.6V, VIH=2.4V
· Output timing voltage : V
OL=1.5V, VOH=1.5V