Datasheet

M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics
Rev.2.41 Jan 10, 2006 Page 72 of 96
REJ03B0001-0241
VCC1=VCC2=3V
Switching Characteristics
(V
CC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
NOTES:
1. Calculated according to the BCLK frequency as follows:
2. Calculated according to the BCLK frequency as follows:
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
4. Calculated according to the BCLK frequency as follows:
Table 5.48 Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Symbol Parameter
Standard
Unit
Min. Max.
t
d(BCLK-AD) Address Output Delay Time
See
Figure 5.12
50 ns
t
h(BCLK-AD) Address Output Hold Time (in relation to BCLK) 4 ns
t
h(RD-AD) Address Output Hold Time (in relation to RD) (NOTE 1) ns
t
h(WR-AD) Address Output Hold Time (in relation to WR) (NOTE 1) ns
t
d(BCLK-CS) Chip Select Output Delay Time 50 ns
t
h(BCLK-CS) Chip Select Output Hold Time (in relation to BCLK) 4 ns
t
h(RD-CS) Chip Select Output Hold Time (in relation to RD) (NOTE 1) ns
t
h(WR-CS) Chip Select Output Hold Time (in relation to WR) (NOTE 1) ns
t
d(BCLK-RD) RD Signal Output Delay Time 40 ns
t
h(BCLK-RD) RD Signal Output Hold Time 0 ns
t
d(BCLK-WR) WR Signal Output Delay Time 40 ns
t
h(BCLK-WR) WR Signal Output Hold Time 0 ns
t
d(BCLK-DB) Data Output Delay Time (in relation to BCLK) 50 ns
t
h(BCLK-DB) Data Output Hold Time (in relation to BCLK) 4 ns
t
d(DB-WR) Data Output Delay Time (in relation to WR) (NOTE 2) ns
t
h(WR-DB) Data Output Hold Time (in relation to WR) (NOTE 1) ns
t
d(BCLK-HLDA) HLDA Output Delay Time 40 ns
t
d(BCLK-ALE) ALE Signal Output Delay Time (in relation to BCLK) 25 ns
t
h(BCLK-ALE) ALE Signal Output Hold Time (in relation to BCLK) −4ns
t
d(AD-ALE) ALE Signal Output Delay Time (in relation to Address) (NOTE 3) ns
t
h(AD-ALE) ALE Signal Output Hold Time (in relation to Address) (NOTE 4) ns
t
d(AD-RD) RD Signal Output Delay From the End of Address 0 ns
t
d(AD-WR) WR Signal Output Delay From the End of Address 0 ns
t
dz(RD-AD) Address Output Floating Start Time 8 ns
0.5x10
9
fBCLK
()
------------------------10ns[]–
0.5x10
9
fBCLK
()
------------------------ 50 ns[]–
0.5x10
9
fBCLK
()
------------------------ 40 ns[]–
0.5x10
9
fBCLK
()
------------------------15ns[]–