Datasheet

M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics
Rev.2.41 Jan 10, 2006 Page 71 of 96
REJ03B0001-0241
VCC1=VCC2=3V
Switching Characteristics
(V
CC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
NOTES:
1. Calculated according to the BCLK frequency as follows:
2. Calculated according to the BCLK frequency as follows:
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t =
−CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when V
OL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t =
−30pF X 1kΩ X In(1−0.2VCC2 / VCC2)
= 6.7ns.
Table 5.47 Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Symbol Parameter
Standard
Unit
Min. Max.
t
d(BCLK-AD) Address Output Delay Time
See
Figure 5.12
30 ns
t
h(BCLK-AD) Address Output Hold Time (in relation to BCLK) 4 ns
t
h(RD-AD) Address Output Hold Time (in relation to RD) 0 ns
t
h(WR-AD) Address Output Hold Time (in relation to WR) (NOTE 2) ns
t
d(BCLK-CS) Chip Select Output Delay Time 30 ns
t
h(BCLK-CS) Chip Select Output Hold Time (in relation to BCLK) 4 ns
t
d(BCLK-ALE) ALE Signal Output Delay Time 25 ns
t
h(BCLK-ALE) ALE Signal Output Hold Time -4 ns
t
d(BCLK-RD) RD Signal Output Delay Time 30 ns
t
h(BCLK-RD) RD Signal Output Hold Time 0 ns
t
d(BCLK-WR) WR Signal Output Delay Time 30 ns
t
h(BCLK-WR) WR Signal Output Hold Time 0 ns
t
d(BCLK-DB) Data Output Delay Time (in relation to BCLK) 40 ns
t
h(BCLK-DB) Data Output Hold Time (in relation to BCLK)
(3)
4ns
t
d(DB-WR) Data Output Delay Time (in relation to WR) (NOTE 1) ns
th(WR-DB) Data Output Hold Time (in relation to WR)
(3)
(NOTE 2) ns
t
d(BCLK-HLDA) HLDA Output Delay Time 40 ns
n0.5–()x10
9
fBCLK
()
------------------------------------ 4 0 n s[]–
0.5x10
9
fBCLK
()
------------------------10ns[]–
DBi
R
C
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.