Datasheet

M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics
Rev.2.41 Jan 10, 2006 Page 63 of 96
REJ03B0001-0241
Figure 5.10 Timing Diagram (8)
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection)
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
th(BCLK-ALE)
−4ns.min
RD
25ns.max
th(BCLK-RD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(RD-CS)
th(RD-AD)
BHE
ADi
/DBi
th(RD-DB)
0ns.min
td(AD-ALE)
Read timing
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
25ns.max
th(BCLK-ALE)
−4ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(WR-AD)
BHE
td(BCLK-DB)
40ns.max
4ns.min
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
ADi
/DBi
Data output
WR,WRL,
WRH
Write timing
Address
(0.5×tcyc-10)ns.min
Address
Data input
40ns.min
(0.5×tcyc-10)ns.min
td(BCLK-ALE)
td(BCLK-RD)
(0.5×tcyc-10)ns.min
th(WR-CS)
Address
td(AD-ALE)
(0.5×tcyc-25)ns.min
(1.5×tcyc-40)ns.min
(0.5×tcyc-10)ns.min
td(BCLK-ALE)
(0.5×tcyc-25)ns.min
Address
25ns.max
tsu(DB-RD)
tac3(RD-DB)
(0.5×tcyc-10)ns.min
td(AD-RD)
0ns.min
tdZ(RD-AD)
8ns.max
td(AD-WR)
0ns.min
Measuring conditions
· V
CC1=VCC2=5V
· Input timing voltage : V
IL=0.8V, VIH=2.0V
· Output timing voltage : V
OL=0.4V, VOH=2.4V
th(ALE-AD)
(1.5×t
cyc-45)ns.max
(0.5×tcyc-15)ns.min
VCC1=VCC2=5V