Datasheet

M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics
Rev.2.41 Jan 10, 2006 Page 50 of 96
REJ03B0001-0241
VCC1=VCC2=5V
Timing Requirements
(V
CC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
NOTES:
1. The condition is VCC1=VCC2=3.0 to 5.0V.
NOTES:
1. Calculated according to the BCLK frequency as follows:
2. Calculated according to the BCLK frequency as follows:
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
n is “2” for 2-wait setting, “3” for 3-wait setting.
Table 5.13 External Clock Input (XIN input)
(1)
Symbol Parameter
Standard
Unit
Min. Max.
t
c External Clock Input Cycle Time 62.5 ns
t
w(H) External Clock Input HIGH Pulse Width 25 ns
t
w(L) External Clock Input LOW Pulse Width 25 ns
t
r External Clock Rise Time 15 ns
t
f External Clock Fall Time 15 ns
Table 5.14 Memory Expansion Mode and Microprocessor Mode
Symbol Parameter
Standard
Unit
Min. Max.
t
ac1(RD-DB) Data Input Access Time (for setting with no wait) (NOTE 1) ns
t
ac2(RD-DB) Data Input Access Time (for setting with wait) (NOTE 2) ns
t
ac3(RD-DB) Data Input Access Time (when accessing multiplex bus area) (NOTE 3) ns
t
su(DB-RD) Data Input Setup Time 40 ns
t
su(RDY-BCLK) RDY Input Setup Time 30 ns
t
su(HOLD-BCLK) HOLD Input Setup Time 40 ns
t
h(RD-DB) Data Input Hold Time 0 ns
t
h(BCLK-RDY) RDY Input Hold Time 0 ns
t
h(BCLK-HOLD) HOLD Input Hold Time 0 ns
0.5x10
9
fBCLK
()
------------------------45ns[]–
n0.5–()x10
9
fBCLK
()
-------------------------------------45ns[]–
n0.5–()x10
9
fBCLK
()
-------------------------------------45ns[]–