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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 16-Bit 24 MHz I/O number 85

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (103 pages)

PAGE 1
To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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M16C/62P Group (M16C/62P, M16C/62PT) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. REJ03B0001-0241 Rev.2.41 Jan 10, 2006 Overview The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency.
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M16C/62P Group (M16C/62P, M16C/62PT) 1.2 1. Overview Performance Outline Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version). Table 1.1 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version) Item CPU Peripheral Function Number of Basic Instructions Minimum Instruction Execution Time Operating Mode Address Space 91 instructions 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.2 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version) Item CPU 1. Overview Number of Basic Instructions Minimum Instruction Execution Time Operating Mode Performance M16C/62P M16C/62PT(4) 91 instructions 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.3 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version) Item CPU 1. Overview Number of Basic Instructions Minimum Instruction Execution Time Operating Mode Address Space Performance M16C/62P M16C/62PT(4) 91 instructions 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Single-chip mode 1 Mbyte See Table 1.4 to 1.
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M16C/62P Group (M16C/62P, M16C/62PT) 1.3 1. Overview Block Diagram Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram, Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram.
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M16C/62P Group (M16C/62P, M16C/62PT) 1.
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M16C/62P Group (M16C/62P, M16C/62PT) 1.4 1. Overview Product List Table 1.4 to 1.7 list the product list, Figure 1.3 shows the Type No., Memory Size, and Package, Table 1.8 lists the Product Code of Flash Memory version and ROMless version for M16C/62P, and Table 1.9 lists the Product Code of Flash Memory version for M16C/62PT. Figure 1.4 shows the Marking Diagram of Flash Memory version and ROM-less version for M16C/62P (Top View), and Figure 1.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.5 1. Overview Product List (2) (M16C/62P) Type No.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.6 1. Overview Product List (3) (T version (M16C/62PT)) Type No.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.7 1. Overview Product List (4) (V version (M16C/62PT)) Type No.
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M16C/62P Group (M16C/62P, M16C/62PT) Type No. 1. Overview M3062 6 MH P - XXX FP Package type: FP : Package GP : Package PRQP0100JB-A (100P6S-A) PRQP0080JA-A (80P6S-A), PLQP0100KB-A (100P6Q-A), PLQP0128KB-A (128P6Q-A), ROM No.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P Product Code Flash memory Version 1.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.9 Product Code of Flash Memory version for M16C/62PT Product Code T Version Flash memory Version 1.
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M16C/62P Group (M16C/62P, M16C/62PT) 1.5 1. Overview Pin Configuration Figures 1.6 to 1.9 show the Pin Configuration (Top View).
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.10 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.11 Pin No. 1.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.12 Pin No. 1.
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M16C/62P Group (M16C/62P, M16C/62PT) 1.
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M16C/62P Group (M16C/62P, M16C/62PT) 1.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.13 1. Overview Pin Characteristics for 100-Pin Package (1) Pin No.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.14 1. Overview Pin Characteristics for 100-Pin Package (2) Pin No.
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M16C/62P Group (M16C/62P, M16C/62PT) 1.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.15 Pin No. 1.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.16 Pin No. 1.
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M16C/62P Group (M16C/62P, M16C/62PT) 1.6 1. Overview Pin Description Table 1.17 Signal Name Power supply input Analog power supply input Reset input Pin Description (100-pin and 128-pin Version) (1) Pin Name VCC1,VCC2 VSS AVCC AVSS I/O Power Description Type Supply(3) I − Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC1 ≥ VCC2. (1, 2) I VCC1 Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.18 Signal Name Main clock input Main clock output Sub clock input Sub clock output BCLK output (2) Clock output 1. Overview Pin Description (100-pin and 128-pin Version) (2) Pin Name XIN XOUT I/O Power Description Type Supply(1) I VCC1 I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (3). To use O VCC1 the external clock, input the clock from XIN and leave XOUT open.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.19 Signal Name Reference voltage input A/D converter Pin Description (100-pin and 128-pin Version) (3) Pin Name VREF AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7 ADTRG ANEX0 D/A converter I/O port Input port I : Input 1.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.20 Signal Name Power supply input Analog power supply input Reset input CNVSS Main clock input Main clock output Sub clock input Sub clock output Clock output 1. Overview Pin Description (80-pin Version) (1) (1) Pin Name I/O Type I Power Supply − AVCC AVSS I VCC1 Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 1.21 Signal Name Reference voltage input A/D converter Pin Description (80-pin Version) (2) Pin Name VREF AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7 ADTRG ANEX0 D/A converter I/O port (1) Input port I : Input 1.
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M16C/62P Group (M16C/62P, M16C/62PT) 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
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M16C/62P Group (M16C/62P, M16C/62PT) 2.2 2. Central Processing Unit (CPU) Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 2.
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M16C/62P Group (M16C/62P, M16C/62PT) 2.8.8 2. Central Processing Unit (CPU) Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”. The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.
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M16C/62P Group (M16C/62P, M16C/62PT) 3. 3. Memory Memory Figure 3.1 is a Memory Map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh. As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for storing data.
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M16C/62P Group (M16C/62P, M16C/62PT) 4. 4. Special Function Register (SFR) Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.6 list the SFR information. Table 4.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 4.2 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 4.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h to 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01C0h to 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h to 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh 4.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 4.4 Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh 4.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 4.5 Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh 4.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 4.6 Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh 4.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. 5. Electrical Characteristics Electrical Characteristics 5.1 Electrical Characteristics (M16C/62P) Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.2 Recommended Operating Conditions (1) (1) Symbol VCC1, VCC2 AVCC VSS AVSS VIH VIL 5. Electrical Characteristics Parameter Supply Voltage (VCC1 ≥ VCC2) Analog Supply Voltage Supply Voltage Analog Supply Voltage P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, HIGH Input P12_0 to P12_7, P13_0 to P13_7 Voltage LOW Input Voltage Min. 2.7 Standard Typ. 5.0 VCC1 0 0 Max. 5.5 Unit 0.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Recommended Operating Conditions (2) (1) Table 5.3 Symbol Parameter Main Clock Input Oscillation Frequency (2) f(XIN) Min. 0 0 VCC1=3.0V to 5.5V VCC1=2.7V to 3.0V f(XCIN) f(Ring) f(PLL) Sub-Clock Oscillation Frequency On-chip Oscillation Frequency PLL Clock Oscillation Frequency (2) 0.5 10 10 VCC1=3.0V to 5.5V VCC1=2.7V to 3.0V f(BCLK) tSU(PLL) CPU Operation Clock PLL Frequency Synthesizer Stabilization Wait Time Standard Typ.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.4 A/D Conversion Characteristics (1) Symbol − INL − − DNL − − RLADDER tCONV tCONV tSAMP VREF VIA 5.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.5 D/A Conversion Characteristics (1) Symbol − − tSU RO IVREF 5. Electrical Characteristics Parameter Resolution Absolute Accuracy Setup Time Output Resistance Reference Power Supply Input Current Measuring Condition Min. 4 (NOTE 2) Standard Typ. 10 Max. 8 1.0 3 20 1.5 Unit Bits % µs kΩ mA NOTES: 1. Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified. 2.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.6 Flash Memory Version Electrical Characteristics (1) for 100 cycle products (D3, D5, U3, U5) Symbol − Parameter Program and Erase Endurance (3) Word Program Time (VCC1=5.0V) Lock Bit Program Time Block Erase Time (VCC1=5.0V) − − − − − − − 5. Electrical Characteristics Min. 100 Table 5.7 − − tPS − 200 200 4 4 4 4 4×n 15 10 Parameter Program and Erase Endurance (3, 8, 9) Word Program Time (VCC1=5.0V) Lock Bit Program Time Block Erase Time (VCC1=5.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.9 Low Voltage Detection Circuit Electrical Characteristics Symbol Vdet4 Vdet3 Vdet4-Vdet3 Vdet3s Vdet3r 5. Electrical Characteristics Parameter Low Voltage Detection Voltage (1) Reset Level Detection Voltage (1, 2) Electric potential difference of Low Voltage Detection and Reset Level Detection Low Voltage Reset Retention Voltage Low Voltage Reset Release Voltage (3) Measuring Condition VCC1=0.8V to 5.5V Min. 3.3 2.2 0.3 2.2 Standard Typ. 3.8 2.8 Max.
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M16C/62P Group (M16C/62P, M16C/62PT) 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.12 Electrical Characteristics (2) (1) Symbol ICC 5. Electrical Characteristics Parameter Measuring Condition Power Supply Current In single-chip (VCC1=VCC2=4.0V to 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.13 External Clock Input (XIN input) (1) Symbol Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time tc tw(H) tw(L) tr tf Standard Min. 62.5 25 25 Max.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.15 Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) Table 5.16 Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Table 5.17 Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.21 Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.28 Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Symbol Standard Min. Max.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.29 Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Symbol Standard Min. Max.
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M16C/62P Group (M16C/62P, M16C/62PT) 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi tsu(D-C) td(C-Q) RXDi tw(INL) INTi input tw(INH) Figure 5.4 Timing Diagram (2) Rev.2.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY−BCLK) th(BCLK−RDY) (Common to setting with wait and setting without wait) BCLK th(BCLK−HOLD) tsu(HOLD−BCLK) HOLD input HLDA input td(BCLK−HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 td(BCLK−HLDA) Hi−Z (1) NOTES: 1.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 25ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 × tcyc-45)ns.max Hi-Z DBi tsu(DB-RD) th(RD-DB) 40ns.min 0ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) 0ns.min th(BCLK-ALE) 25ns.max -4ns.min ALE td(BCLK-RD) th(BCLK-RD) 25ns.max 0ns.min RD tac2(RD-DB) (1.5 × tcyc-45)ns.max Hi-Z DBi th(RD-DB) tsu(DB-RD) 0ns.min 40ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (for 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(RD-AD) th(BCLK-ALE) 0ns.min -4ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 25ns.max RD tac2(RD-DB) (2.5×tcyc-45)ns.max DBi Hi-Z tsu(DB-RD) 40ns.min th(RD-DB) 0ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) td(BCLK-CS) 25ns.max 4ns.min CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 25ns.max 0ns.min -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 25ns.max 0ns.min RD tac2(RD-DB) (3.5×tcyc-45)ns.max Hi-Z DBi tsu(DB-RD) th(RD-DB) 40ns.min 0ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplex bus selection ) Read timing BCLK td(BCLK-CS) th(BCLK-CS) th(RD-CS) (0.5×tcyc-10)ns.min tcyc 25ns.max 4ns.min CSi td(AD-ALE) th(ALE-AD) (0.5×tcyc-25)ns.min (0.5×tcyc-15)ns.min ADi /DBi Address 8ns.max Address Data input tdZ(RD-AD) tac3(RD-DB) (1.5×tcyc-45)ns.max tsu(DB-RD) th(RD-DB) 0ns.min 40ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection ) Read timing tcyc BCLK th(RD-CS) (0.5×tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 4ns.min 25ns.max CSi td(AD-ALE) th(ALE-AD) (0.5×tcyc-25)ns.min ADi /DBi (0.5×tcyc-15)ns.min Address Data input th(RD-DB) tdZ(RD-AD) td(BCLK-AD) 8ns.max td(AD-RD) 25ns.max (2.5×tcyc-45)ns.max 0ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Table 5.30 Electrical Characteristics (1) Symbol VOH VOH Parameter HIGH Output Voltage (3) IOH=−1mA P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOH=−1mA (2) HIGH Output Voltage VOL LOW Output Voltage (3) XOUT XCOUT IOH=−0.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.31 Electrical Characteristics (2) (1) Symbol ICC 5. Electrical Characteristics Parameter Measuring Condition Power Supply Current In single-chip (VCC1=VCC2=2.7V to 3.6V) mode, the output pins are open and other pins are VSS Mask ROM Flash Memory Flash Memory Program Flash Memory Erase Mask ROM Flash Memory Idet4 Idet3 (4) Low Voltage Detection Dissipation Current Reset Area Detection Dissipation Current (4) Standard Typ. Max.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.32 External Clock Input (XIN input)(1) Symbol Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time tc tw(H) tw(L) tr tf Standard Min. Max.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.34 Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) Table 5.35 Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Table 5.36 Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.47 Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Symbol Standard Min. Max.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.48 Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Symbol Standard Min. Max.
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M16C/62P Group (M16C/62P, M16C/62PT) 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi tsu(D-C) td(C-Q) RXDi tw(INL) INTi input tw(INH) Figure 5.14 Timing Diagram (2) Rev.2.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode VCC1=VCC2=3V (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY−BCLK) th(BCLK−RDY) (Common to setting with wait and setting without wait) BCLK th(BCLK−HOLD) tsu(HOLD−BCLK) HOLD input HLDA output td(BCLK−HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 (1) td(BCLK−HLDA) Hi−Z NOTES: 1.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Memory Expansion Mode, Microprocessor Mode (for setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 30ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 × tcyc-60)ns.max Hi-Z DBi tsu(DB-RD) 50ns.min th(RD-DB) 0ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Read timing BCLK td(BCLK−CS) th(BCLK−CS) 30ns.max 4ns.min CSi tcyc td(BCLK−AD) th(BCLK−AD) 30ns.max 4ns.min ADi BHE td(BCLK−ALE) th(RD−AD) th(BCLK−ALE) 0ns.min −4ns.min 30ns.max ALE td(BCLK−RD) th(BCLK−RD) 30ns.max 0ns.min RD tac2(RD−DB) (1.5 × tcyc−60)ns.max Hi−Z DBi th(RD−DB) tsu(DB−RD) 0ns.min 50ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Memory Expansion Mode, Microprocessor Mode (for 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 30ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 30ns.max ADi BHE td(BCLK-ALE) 30ns.max th(RD-AD) 0ns.min th(BCLK-ALE) -4ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 30ns.max RD tac2(RD-DB) (2.5 × tcyc-60)ns.max Hi-Z DBi tsu(DB-RD) 50ns.min th(RD-DB) 0ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1 = VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) td(BCLK-CS) 4ns.min 30ns.max CSi th(BCLK-AD) td(BCLK-AD) 4ns.min 30ns.max ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 30ns.max 0ns.min -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 0ns.min 30ns.max RD tac2(RD-DB) (3.5 × tcyc-60)ns.max Hi-Z DBi tsu(DB-RD) th(RD-DB) 50ns.min 0ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode VCC1=VCC2=3V (For 2-wait setting, external area access and multiplex bus selection) Read timing BCLK td(BCLK-CS) th(BCLK-CS) th(RD-CS) (0.5×tcyc-10)ns.min tcyc 40ns.max 4ns.min CSi td(AD-ALE) (0.5×tcyc-40)ns.min ADi /DBi th(ALE-AD) (0.5×tcyc-15)ns.min Address 8ns.max Address Data input tdZ(RD-AD) tac3(RD-DB) (1.5×tcyc-60)ns.max tsu(DB-RD) th(RD-DB) 0ns.min 50ns.min td(AD-RD) 0ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection) Read timing tcyc BCLK th(RD-CS) (0.5×tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 6ns.min 40ns.max CSi td(AD-ALE) (0.5×tcyc-40)ns.min th(ALE-AD) (0.5×tcyc-15)ns.min ADi /DBi Data input Address td(BCLK-AD) 40ns.max tac3(RD-DB) 8ns.max td(AD-RD) (2.5×tcyc-60)ns.max 0ns.
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M16C/62P Group (M16C/62P, M16C/62PT) 5.2 5. Electrical Characteristics Electrical Characteristics (M16C/62PT) Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) Recommended Operating Conditions (1) (1) Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.51 A/D Conversion Characteristics (1) Symbol − INL − Parameter Resolution Integral Non-Linearity Error Absolute Accuracy − DNL − − RLADDER tCONV tCONV tSAMP VREF VIA 5.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.53 5. Electrical Characteristics Flash Memory Version Electrical Characteristics (1) for 100 cycle products (B, U) Symbol Parameter − Program and Erase Endurance (3) Word Program Time (VCC1=5.0V) Lock Bit Program Time Block Erase Time (VCC1=5.0V) − − − − − − − tPS − Min. 100 4-Kbyte block 8-Kbyte block 32-Kbyte block 64-Kbyte block Erase All Unlocked Blocks Time (2) Flash Memory Circuit Stabilization Wait Time Data Hold Time (5) Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.56 Power Supply Circuit Timing Characteristics Symbol td(P-R) td(R-S) td(W-S) 5. Electrical Characteristics Parameter Measuring Condition Time for Internal Power Supply Stabilization During Powering-On STOP Release Time Low Power Dissipation Mode Wait Mode Release Time Standard Typ. VCC1=4.0V to 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) Table 5.58 Electrical Characteristics (2) (1) Symbol ICC 5. Electrical Characteristics Parameter Power Supply Current In single-chip (VCC1=VCC2=4.0V to 5.5V) mode, the output pins are open and other pins are VSS Measuring Condition Mask ROM f(BCLK)=24MHz No division, PLL operation No division, On-chip oscillation Flash Memory Flash Memory Program Flash Memory Erase Mask ROM Flash Memory Standard Typ. Max.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise specified) Table 5.59 External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Rev.2.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise specified) Table 5.60 Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) Table 5.61 Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise specified) Table 5.66 Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Table 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise specified) P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Figure 5.23 Ports P0 to P10 Measurement Circuit Rev.2.
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M16C/62P Group (M16C/62P, M16C/62PT) 5.
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M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi tsu(D-C) td(C-Q) RXDi tw(INL) INTi input tw(INH) Figure 5.25 Timing Diagram (2) Rev.2.
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M16C/62P Group (M16C/62P, M16C/62PT) Appendix 1. Package Dimensions Appendix 1.Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP128-14x20-0.50 PLQP0128KB-A 128P6Q-A 0.9g HD *1 D 102 65 103 64 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp c *2 E HE c1 b1 Reference Symbol ZE Terminal cross section Dimension in Millimeters Min Nom Max D 19.9 20.0 20.1 E 13.9 14.0 14.
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M16C/62P Group (M16C/62P, M16C/62PT) JEITA Package Code RENESAS Code P-LQFP100-14x14-0.50 PLQP0100KB-A Appendix 1. Package Dimensions Previous Code MASS[Typ.] 100P6Q-A / FP-100U / FP-100UV 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 50 76 bp c1 Reference Symbol c E *2 HE b1 Terminal cross section 26 Nom 13.9 14.0 14.1 E 13.9 14.0 14.1 HD 15.8 16.0 16.2 HE 15.8 16.0 16.2 A1 0.05 0.
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REVISION HISTORY Rev. Date 1.10 May 28, 2003 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Page Summary 1 Applications are partly revised. 2 Table 1.1.1 is partly revised. 4-5 Table 1.1.2 and 1.1.3 is partly revised. “Note 1” is partly revised. 22 23 Table 1.5.3 is partly revised. Table 1.5.5 is partly revised. Table 1.5.6 is added. 24 30 31 Table 1.5.9 is partly revised. Notes 1 and 2 in Table 1.5.26 is partly revised. Notes 1 in Table 1.5.27 is partly revised.
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REVISION HISTORY Rev. Date M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Page Summary Table 5.4 A-D Conversion Characteristics is revised. Table 5.5 D-A Conversion Characteristics revised. 34,74 Table 5.6 to 5.7 and table 5.54 to 5.55 are revised. Table 5.11 is revised. 36 38,55 Table 5.14 and 5.33 HLDA output deley time is deleted. Figure 5.1 is partly revised. 41 41-43, Table 5.27 to 5.29 and table 5.46 to 48 HLDA output deley time is added. 58-60 Figure 5.
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REVISION HISTORY Rev. Date Description Page 40 57 70 72 73 74 76 79 2.41 Jan 01, 2006 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 2-4 Summary Table 5.24 is partly revised. Table 5.43 is partly revised. Table 5.48 is partly revised. Table 5.50 is partly revised. Table 5.53 is partly revised. Table 5.55 is revised. Table 5.57 is partly revised. Table 5.69 is partly revised. voltage down detection reset -> brown-out detection Reset Tables 1.1 to 1.
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REVISION HISTORY Rev. Date M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Page Summary 47 Figure 5.1 Power Supply Circuit Timing Diagram is partly revised. 48 Table 5.11 Electrical Characteristics (1) is partly deleted. 49 Table 5.12 Electrical Characteristics (2) is partly revised. 50 Note 1 of Table 5.13 External Clock Input (XIN input) is added. 67 Notes 1 to 4 of Table 5.32 External Clock Input (XIN input) are added. 85 Table 5.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.