Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 16-Bit 20 MHz I/O number 71

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REVISION HISTORY M16C/29 Hardware Manual

Rev. Date Description

Page Summary

C-10

258 • Figure 16.3 S00 Register Note is modified

259 • Figure 16.4 S1D0 Register Reserved bit map modified

260 • Figure 16.5 S10 Register b7-b6 modified

262 • Figure 16.7 S4D0 Register Bit reserved map is modified

269 • 16.5.1 Bit 0: Last Receive Bit (LRB) modified

• 16.5.2 Bit 1: General call detection flag (ADR0) modified, note 1 modified

• 16.5.3 Bit 2: Slave address comparison flag (AAS) modified

270 • 16.5.5 Bit 4: I

C Bus Interface Interrupt Request Bit (PIN) modified

• 16.5.6 Bit 5: Bus Busy Flag (BB) Bit names are modified

271 • 16.5.8 Bit 7: Communication Mode Select bit (MST) modified

276 • 16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) is modified

• 16.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN) is

modified

279 • 16.11 Stop Condition Generation Method Description added

282 • 16.13 Address Data Communication modified

CAN Module

292 • Figure 17.6 C0MCTLj Register RspLock bit’s name changed, note 2 revised

293 • Figure 17.7 C0CTLR Register Note 4 added, functions partially modified

294 • Figure 17.8 C0STR Register Note 1 deleted, functions partially modified

298 • Figure 17.13 C0RECR Register Note 2 deleted, note 1 partially modified

• Figure 17.14 C0TECR Register Note 1 modified, note is relocated

299 • Figure 17.15 C0TSR Register Note 1 modified

300 • Figure 17.17 Transition Between Operational Modes Partially modified

301 • 17.2.3 CAN Sleep Mode Partially deleted

304 • Table 17.2 Example of Bit-Rate 24-MHz is deleted

308 • 17.8 Time Stamp Counter and Time Stamp Function Partially deleted

310 • Figure 17.25 Timing of Receive Data Frame Sequence IF to IFS

311 • Figure 17.26 Timing of Transmit Sequence IF to IFS

CRC Calculation Circuit

313 • 18.1 CRC Snoop Description partially added

Programmable I/O Ports

316 • Note added

• 19.3 Pull-up Control Register 0 to 2 Description partially added

317 • 19.6 Digital Debounce Function Filter width formula modified

318-321 • Figure 19.1 I/O Ports (1) to Figure 19.4 I/O Ports (4) are modified

326 • Figure 19.10 PACR Register Note 1 is modified

327 •

Figure 19.11 NDDR and P17DDR Register Functions modified, notes are added

328 • Figure 19.12 Functioning of Digital Debounce Filter modified, procedure note

modified