Datasheet
REVISION HISTORY M16C/29 Hardware Manual
Rev. Date Description
Page Summary
C-9
214 • Figure 14.31 Transmit and Received Timing in SIM Mode partially modified
217 • 14.2 SI/O3 and SI/O4 Note added
218 • Figure 14.36 S3C and S4C Registers Note 5 is added
• Figure 14.36 S3BRG and S4BRG Registers Note 3 is added
220 • Figure 14.38 Polarity of Transfer Clock figure modified
221 • 14.2.3 Functions for Setting an SOUTi Initial Value Description modified
A/D Converter
222 • Note added
• Table 15.1 A/D Converter Performance Integral Nonlinearity Error modified
224 • Figure 15.2 ADCON2 Registers b2-b1 function modified
227 • Figure 15.5 TB2SC Register Reserved bit map modified
229 • Figure 15.7 ADCON0 to ADCON2 Registers in One-shot Mode ADCON2
register: b2-b1 function modified
231 • Figure 15.9 ADCON0 to ADCON2 Registers in Repeat Mode ADCON2 regis-
ter: b2-b1 function modified
233 • Figure 15.11 ADCON0 to ADCON2 Registers in Single Sweep Mode
ADCON2 register: b2-b1 function modified
235 • Figure 15.13 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 0
ADCON2 register: b2-b1 function modified
237 • Figure 15.15 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 1
ADCON2 register: b2-b1 function modified
239 • Figure 15.17 ADCON0 to ADCON2 Registers in Simultaneous Sample
Sweep Mode ADCON2 register: b2-b1 function modified
241 • Table 15.10 Delayed Trigger Mode 1 Specifications Note 1 is modified
245 • Figure 15.22 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 0
ADCON2 register: b2-b1 function modified
251 • Figure 15.27 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 1
ADCON2 register: b2-b1 function modified
254 • 15.5 Analog Input Pin and External Sensor Equivalent Circuit Example is
deleted
• 15.5 Output Impedance of Sensor under A/D Conversion is added
• Figure 15.29 Analog Input Pin and External Sensor Equivalent Circuit Note
1 is added
- • Precaution of Using A/D Converter deleted
Multi-master I
2
C bus INTERFACE
255 • Table 16.1 Multi-master I
2
C bus Interface Functions I/O pin added
256 • Figure 16.1 Block Diagram of Multi-master I
2
C bus Interface Bit name and
register name are modified
257 • Figure 16.2 S0D0 Register Bit map is modified