Datasheet
REVISION HISTORY M16C/29 Hardware Manual
Rev. Date Description
Page Summary
C-7
63 •
Figure 7.11 State Transition to Stop Mode and Wait Mode modified, Note 7 is added
64 • Figure 7.12 State Transition in Normal Mode modified, note 5 deleted, note 6
and 7 are simplified
65 • Table 7.7 Allowed Transition and Setting note 2 partially modified, table con
tents are partially modified
68 • Figure 7.13 Procedure to Switch Clock Source From On-chip Oscillator
Clock to Main Clock is modified
Interrupt
70 • Note is newly added
73 • Table 9.1 Fixed Vector Tables Note 2 is added
Watchdog Timer
89 • Additional information of the WDTS register is inserted
90 •
Figure 10.1 Watchdog Timer Block Diagram modified
•
Figure 10.2 WDC Register and WDTS Register All notes are deleted
-
• 10.2 Cold Start/Warm Start Section is deleted
DMAC
96 • Note is added
Timer
105 • Figure 12.6 TRGSR Register Note 2 added
117 • 12.2 Timer B Description of A/D trigger mode modified
• Figure 12.15 Timer B Block Diagram “A/D trigger mode” is added
123 • 12.2.4 A/D Trigger Mode Description modified
129 • Figure 12.28 IDB0 Register, IDB1 Register, DTT Register, and ICTB2 Regis-
ter Information of bit 7 and 6 modified
131 • Figure 12.30 TB2SC Register Note 4 added, contents modified
133 • Figure 12.32 TA1MR Register, TA2MR Register, TA4MR Register MR0 bit is
modified
134 • Figure 12.33 Triangular Wave Modulation Operation Description modified
135 • Figure 12.34 Sawtooth Wave Modulation Operation Description modified
139 • Figure 12.38 TPRC Register Bit map is modified
Timer S
142 • Figure 13.2 G1BT and G1BCR0 Registers Function of G1BT register modified,
note 3 is added, function of bits 5 to 3 modified, description patially modified
143 • Figure 13.3 G1BCR1 Register Note 1 is partially added
146 • Figure 13.6 G1TM0 to G1TM7 Registers Note 3 and 4 are added
151-166 • Table 13.2, 13.5, 13,8, 13.9 and 13.10 Output wave form and Selectable func-
tion are modified
155 • Figure 13.15 Base Timer Reset Operation by Base Timer Reset Register
Base timer overflow request line is added, base timer interrupt line is modified,