Datasheet

REVISION HISTORY M16C/29 Hardware Manual
Rev. Date Description
Page Summary
C-6
Overview
2 Table 1.1 and 1.2 Performance Outline Voltage detection circuit are modified,
note 3 is modified
4 - 5 Figure 1.1 and 1.2 Block Diagrams are updated
6 - 7 Table 1.3 to 1.5 Product Lists are updated
8 Figure 1.3 Produt Numbering System is modified
9 Tables 1.6 to 1.8 Product Code B3, B7, D3, D5, D7, D9 are deleted
Tables 1.9 to 1.11 Product Code Mask ROM versions are newly added
13 - 17
Table 1.9 and 1.10 Pin Characteristics for 80-, and 64-pin Packages are added
18 Table 1.11 Pin Description Tables are modified
Memory
23 Figure 3.1 Memory Map 48Kbyte memory size is deleted
Special Function Register
24 - 34 Table 4.1 to 4.11 SFR Information values after reset
24 Table 4.1 SFR Information(1) Note 3 is deleted
Reset
35 5.1.2 Hardware Reset 2 Note is modified, description is modified
38 5.5 Voltage Dection Circuit modified
Figure 5.4 Voltage Detection Circuit Block modified, WDC5 bit circuit deleted
Processor Mode
44 Figure 6.1 PM1 Register Note 2 information partially added
45 Figure 6.2 PM2 Register added
46 Figure 6.3 Bus Block Diagram and Table 6.1 Accessible Area and Bus
Cycle added
Clock Generation Circuit
47 Table 7.1 Clock Generation Circuit Specifications Oscillation stop, restart
function modified
48 Figure 7.1 Clock Generation Circuit Upper portion of figure is modified
50 Figure 7.4 ROCR Register Bit conents are modified
52 Figure 7.6 PCLKR Register and PM2 Register Note 2 is modified
54 Figure 7.8 Examples of Main Clock Connection Circuit is modified
55 Figure 7.9 Examples of Sub Clock Connection Circuit is modified
7.5.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO,
fAD, fc32, fCAN0) revised
59 7.6.1 Normal Operation Mode Information is modified
60 Table 7.4 Setting Clock Related Bit and Modes Multi-master I2C bus interrupt
and Timer S interrupt added
61 Table 7.5 Pin Status in Wait Mode newly added
Table 7.6 Interrupts to Exit Wait Mode modified