Datasheet

19. Programmable I/O Ports
puorG92/C61M
page 327
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 19.11 NDDR and P17DDR Registers
NMI Digital Debounce Register
(1,2)
Symbol Address After Reset
NDDR 033E
16 FF16
RW
b7 b0
Function
RW
Setting Range
00
16 to FF 16
If the set value =n,
- n = 0 to FE
16; a signal with pulse width, greater than
(n+1)/f8, is input into NMI / SD
- n = FF
16; the digital debounce filter is disabled and all
signals are input
P1 7 Digital Debounce Register
(1)
Symbol Address After Reset
P17DDR 033F
16 FF16
RW
b7 b0
Function
RW
Setting Range
00
16 to FF 16
If the set value =n,
- n = 0 to FE
16; a signal with pulse width, greater than
(n+1)/f8, is input into INPC17/ INT5
- n = FF
16; the digital debounce filter is disabled and all
signals are input
NOTES:
1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to 1 (write
enable).
2. When using the NMI interrupt to exit from stop mode, set the NDDR registert to FF
16 before entering
stop mode.
NOTE:
1. When using the INT5 interrupt to exit from stop mode, set the P17DDR registert to FF
16 before entering
stop mode.