Datasheet

16. MULTI-MASTER I
2
C bus INTERFACE
puorG92/C61M
page 268
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 16.10 The timing of reset to the I
2
C bus interface circuit
A reset signal to I
2
C bus interface circuit
Write 1 to IHR bit
IHR bit
2.5 V IIC cycles
16.4.5 Bit 7: I
2
C bus Interface Pin Input Level Select Bit (TISS)
The TISS bit selects the input level of the SCL and SDA pins for the multi-master I
2
C bus interface.
When the TISS bit is set to 1, the P20 and P21 become the SMBus input level.