Datasheet

16. MULTI-MASTER I
2
C bus INTERFACE
puorG92/C61M
page 257
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 16.2 S0D0 Register
SAD6
SAD5
SAD4
SAD3
SAD2
SAD1
SAD0
Reserved bit
FunctionBit NameBit Symbol
Address After ResetSymbol
C
0 Address Re
g
ister
S0D0 02E2 16 00 16
b
7
b6
b5
b
4
b3
b
2b1b0
I
2
Slave address
Set to 0
Compare with received
address data
RW
RW
RW
RW
RW
RW
RW
RW
RW
(b0)
0