Datasheet

16. MULTI-MASTER I
2
C bus INTERFACE
puorG92/C61M
page 256
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 16.1 Block diagram of multi-master I
2
C bus interface
Serial Data
(SDA)
BB
circuit
Noise
elimination
circuit
(SCL)
b7 b0
ACK
CLK
ACK
BIT
FAST
MODE
CCR4 CCR3 CCR2 CCR1
CCR0
Internal data bus
Clock division
S20
b7
b0
SAD6 SAD5 SAD4
SAD3
SAD2 SAD1
SAD0
Address comparator
b7
b0
S00
S0D0
(S
CL
S
DA
IRQ)
b7 b0
ICK1 ICK0 SCLM SDAM WIT
SIM
S3D0
Interrupt
generation
circui
t
b7
MST TRX BB
PIN
AL AAS AD0
LRB
b0
S10
b7 b0
TISS
ALS BC2
BC1
ES0
I
2
C system clock
(VIIC)
Time-out detection
circuit
TOF TO
E
ICK 4 ICK 3 ICK2
TOSEL
System clock select circut
I
2
C0 Control Register 1
I
2
C0 start/stop condition control register
S2D0
STSP
SEL
SIS
SIP
SSC4
SSC3
SSC2 SSC1 SSC0
I
2
C0 address registers
I
2
C0 data shift registers
I
2
C0 Control Registers 2
S4D0
I
2
C0 clock control registers
I
2
C0 Status Registers
I
2
C0 control registers 0
S1D0
I
2
C bus interface
Interrupt request signal
Bit counter
(I
2
C IRQ)
Serial
clock
BC0
Clock
control
circuit
AL
circuit
Noise
elimination
circuit
Data
control
circuit
Interrupt request signal
Interrupt
generation
circuit
f
1
f
2
PCLK0=1
f
IIC
PCLK0=0