Datasheet

14. Serial I/O
puorG92/C61M
page 179
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2110-1010B90JER
Figure 14.9 U2SMR3 and U2SMR4 Registers
UART2 Special Mode Register 3
Symbol Address After Reset
U2SMR3 0375
16 000X0X0X 2
b7 b6 b5 b4 b3 b2 b1 b0
Bit Name
Bit
Symbol
Function
DL2
SDA
2 digital delay
setup bit
(1, 2)
DL0
DL1
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of U2BRG count source
0 1 0 : 2 to 3 cycles of U2BRG count source
0 1 1 : 3 to 4 cycles of U2BRG count source
1 0 0 : 4 to 5 cycles of U2BRG count source
1 0 1 : 5 to 6 cycles of U2BRG count source
1 1 0 : 6 to 7 cycles of U2BRG count source
1 1 1 : 7 to 8 cycles of U2BRG count source
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
b7 b6 b5
0 : Without clock delay
1 : With clock delay
Clock phase set bit
0 : CLK
2 is CMOS output
1 : CLK
2 is N-channel open drain output
Clock output select bit
CKPH
NODC
RW
RW
RW
RW
RW
RW
(b0)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
(b2)
(b4)
NOTES:
1. Bits DL2 to DL0 are used to generate a delay in SDA output by digital means during I
2
C bus mode. In other than I
2
C bus
mode,set these bits to 000
2 (no delay).
2. The amount of delay varies with the load on pins SCL2 and SDA2. Also, when using an external clock, the amount of
delay increases by about 100 ns.
UART2 Special Mode Register 4
Symbol Address After Reset
U2SMR4 0374
16 00 16
b7 b6 b5 b4 b3 b2 b1 b0
Bit Name
Bit
Symbol
RWFunction
ACKC
SCLHI
SWC9
Start condition
generate bit
(1)
Stop condition
generate bit
(1)
0 : Clear
1 : Start
SCL
2 ,SDA 2 output
select bit
ACK data bit
Restart condition
generate bit
(1)
0 : Clear
1 : Start
0 : Clear
1 : Start
STAREQ
RSTAREQ
STPREQ
ACKD
0 : Start and stop conditions not output
1 : Start and stop conditions output
SCL
2 output stop
enable bit
ACK data output
enable bit
0 : Disabled
1 : Enabled
0 : ACK
1 : NACK
0 : Serial I/O data output
1 : ACK data output
NOTE:
1. Set to 0 when each condition is generated.
STSPSEL
0 : SCL
2 “L” hold disabled
1 : SCL
2 “L” hold enabled
SCL
2 wait bit 3
RW
RW
RW
RW
RW
RW
RW
RW