Datasheet

9. Interrupts
puorG92/C61M
page 77
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 9.4 IFSR Register and IFSR2A Register
Interrupt Request Cause Select Register
Bit Name Function
Bit Symbol
RW
Symbol Address After Reset
IFSR 035F
16 00
16
IFSR0
b7 b6 b5 b4 b3 b2 b1 b0
INT0 interrupt polarity
switching bit
0 : SI/O3
1 : INT4
0 : SI/O4
1 : INT5
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
Interrupt request cause
select bit
Interrupt request cause
select bit
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
RW
RW
RW
RW
RW
RW
RW
RW
(1)
(1)
(1)
(1)
(1)
(1)
(2)
NOTES:
1. When setting this bit to 1 (both edges), make sure the POL bit in registers INT0IC to INT5IC is set to
0 (falling edge).
2. When setting this bit to 0 (SI/O3, SI/O4), make sure the POL bit in registers S3IC and S4IC is set to
0 (falling edge).
(2)
Interrupt Request Cause Select Register 2
Bit Name Function
Bit Symbol
RW
Symbol Address After reset
IFSR2A 035E
16 00XXX000 2
b7 b6 b5 b4 b3 b2 b1 b0
0: IC/OC base timer
1: S
CL /S DA
0: IC/OC interrupt 1
1: I
2
C bus interface
IFSR26
IFSR27
Interrupt request cause
select bit
Interrupt request cause
select bit
RW
RW
Set to 0
(b5-b3)
Nothing is assigned. If necessary, set to 0.
When read, the contents are undefined
IFSR20
0
Reserved bit
RW
IFSR21
IFSR22
Interrupt request cause
select bit
Interrupt request cause
select bit
0: A/D conversion
1: Key input
0: CAN0 wakeup/error
1: Do not set
RW
RW