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To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (501 pages)

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To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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User’s Manual M16C/29 Group 16 Hardware Manual RENESAS MCU M16C FAMILY / M16C/Tiny SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). Rev.1.12 2007.
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Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
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2. Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories.
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3. Register Notation The symbols and terms used in register diagrams are described below. XXX Register b7 b6 b5 b4 b3 *1 b2 b1 b0 Symbol XXX 0 Bit Symbol XXX0 Address XXX Bit Name XXX bits XXX1 After Reset 0016 Function RW 1 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX RW RW (b2) Nothing is assigned. If necessary, set to 0. When read, the content is undefined. (b3) Reserved bits Set to 0. RW XXX bits Function varies according to the operating mode.
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4.
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Table of Contents Quick Reference to Pages Classified by Address _____________________ B-1 1. Overview ____________________________________________________ 1 1.1 Features ........................................................................................................................... 1 1.1.1 Applications ................................................................................................................ 1 1.1.2 Specifications ............................................................
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5. Resets _____________________________________________________ 35 5.1 Hardware Reset .............................................................................................................. 35 5.1.1 Hardware Reset 1 .................................................................................................... 35 5.1.2 Brown-Out Detection Reset (Hardware Reset 2) ..................................................... 35 5.2 Software Reset ..........................................................
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9. Interrupts ___________________________________________________ 70 9.1 Type of Interrupts ............................................................................................................ 70 9.1.1 Software Interrupts ................................................................................................... 71 9.1.2 Hardware Interrupts ................................................................................................. 72 9.2 Interrupts and Interrupt Vector ................
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12. Timers ___________________________________________________ 101 12.1 Timer A ...................................................................................................................... 103 12.1.1 Timer Mode .......................................................................................................... 106 12.1.2 Event Counter Mode ............................................................................................ 107 12.1.3 One-shot Timer Mode ..............................
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.2 SI/O3 and SI/O4 ........................................................................................................ 217 14.2.2 CLK Polarity Selection ........................................................................................ 220 14.2.1 SI/Oi Operation Timing ........................................................................................ 220 14.2.3 Functions for Setting an SOUTi Initial Value ....................................................... 221 15.
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16.5.3 Bit 2: Slave Address Comparison Flag (AAS) ..................................................... 269 16.5.4 Bit 3: Arbitration Lost Detection Flag (AL) ........................................................... 269 16.5.5 Bit 4: I2C bus Interface Interrupt Request Bit (PIN) ............................................. 270 16.5.6 Bit 5: Bus Busy Flag (BB) .................................................................................... 270 16.5.
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17.2 Operating Modes ........................................................................................................ 300 17.2.1 CAN Reset/Initialization Mode ............................................................................. 300 17.2.2 CAN Operating Mode ........................................................................................... 301 17.2.3 CAN Sleep Mode ................................................................................................. 301 17.2.
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20.4 CPU Rewrite Mode ..................................................................................................... 337 20.4.1 EW Mode 0 .......................................................................................................... 338 20.4.2 EW Mode 1 .......................................................................................................... 338 20.5 Register Description ...................................................................................................
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21. Electrical Characteristics _____________________________________ 366 21.1 Normal version ........................................................................................................... 366 21.2 T version ..................................................................................................................... 387 21.3 V Version .................................................................................................................... 408 22.
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22.9 A/D Converter ............................................................................................................. 439 22.10 Multi-Master I2C bus Interface ................................................................................. 441 22.10.1 Writing to the S00 Register ................................................................................ 441 22.10.2 AL Flag ............................................................................................................... 441 22.
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Appendix 1. Package Dimensions ________________________________ 453 Appendix 2. Functional Comparison _______________________________ 454 Appendix 2.1 Difference between M16C/28 Group and M16C/29 Group (Normal-ver.) .... 454 Appendix 2.2 Difference between M16C/28 and M16C/29 Group (T-ver./V-ver.) ...............
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Quick Reference to Pages Classified by Address Address Register Symbol Page Address 000016 004016 000116 004116 000216 004216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 004316 Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 PM0 PM1 CM0 CM1 44 44 49 50 Address match interrupt enable register Protect register AIER PRCR 88 69 Oscillation stop detection register C
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Quick Reference to Pages Classified by Address Address Register Symbol Page Address 008016 00C016 008116 00C116 008216 008316 CAN0 message box 2: Identifier/DLC 00C216 289 00C316 008416 00C416 008516 00C516 008616 00C616 008716 00C716 008816 00C816 008916 008A16 CAN0 message box 2: Data field 00C916 289 00CA16 008B16 00CB16 008C16 00CC16 008F16 CAN0 message box 2: time stamp 00CE16 289 00CF16 CAN0 message box 3: Identifier/DLC 00D216 289 00D316 009416 00D416 00951
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Quick Reference to Pages Classified by Address Address Register Symbol Page Address 010316 CAN0 message box 10: Identifer/DLC 014216 289 014316 010416 014416 010516 014516 010616 014616 010716 014716 010A16 CAN0 message box 10: Data field 014916 289 014A16 010B16 014B16 010C16 014C16 010F16 CAN0 message box 10: time stamp 014E16 289 014F16 011016 015016 011116 015116 011216 011316 CAN0 message box 11: Identifier/DLC 015216 289 015316 011416 015416 011516 015516 0
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Quick Reference to Pages Classified by Address Address Register Symbol Page Address 018016 024016 018116 024116 018216 024216 018316 024316 018416 024416 018516 024516 018616 024616 Register Symbol Page CAN0 acceptance filter support register C0AFS 299 Three-phase protect control register TPRC 139 025F16 0n-chip oscillator control register Pin assignment control register Peripheral clock select register CAN0 clock select register ROCR PACR PCLKR CCLKR 02E016 I2C0 data shift re
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Quick Reference to Pages Classified by Address Register Address 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 Symbol Page TM, WG register 0 G1TM0, G1PO0 146,147 TM, WG register 1 G1TM1, G1PO1 146,147 TM, WG register 2 G1TM2, G1PO2 146,147 TM, W
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Quick Reference to Pages Classified by Address Register Address 038016 Symbol Page 104, 118, 132 03C016 Count start flag TABSR Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag CPSRF ONSF TRGSR UDF Timer A0 register TA0 104 03C716 Timer A1 register TA1 104 03C916 Timer A2 register TA2 104 03CB16 Timer A3 register TA3 104 03CD16 Timer A4 register TA4 104 03CF16 Timer B0 register TB0 118 03D116 Timer B1 register TB1 118 03D316 Timer B2 reg
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M16C/29 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. Overview 1.1 Features The M16C/29 Group of single-chip control MCU incorporates the M16C/60 series CPU core, employing the high-performance silicon gate CMOS technology and sophisticated instructions for a high level of efficiency. The M16C/29 Group is housed in 64-pin and 80-pin plastic molded LQFP packages. These singlechip MCUs operate using sophisticated instructions featuring a high level of instruction efficiency.
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1. Overview M16C/29 Group 1.1.2 Specifications Table 1.1 lists performance overview of M16C/29 Group 80-pin package. Table 1.2 lists performance overview of M16C/29 Group 64-pin package. Table 1.1 Performance Overview of M16C/29 Group (T-ver./V-ver.) (80-Pin Package) Item Performance CPU Number of basic instructions 91 instructions Shortest instruction 50 ns (f(BCLK) = 20MHZ, VCC = 3.0 to 5.5 V) (Normal-ver./T-ver.) excution time 100 ns(f(BCLK) = 10MHZ, VCC = 2.7 to 5.5 V) (Normal-ver.
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1. Overview M16C/29 Group Table 1.2 Performance Overview of M16C/29 Group (64-Pin Package) Item Performance CPU Number of basic instructions 91 instructions Shortest instruction 50 ns (f(BCLK) = 20MHZ, VCC = 3.0 to 5.5 V) (Normal-ver./T-ver.) excution time 100 ns(f(BCLK) = 10MHZ, VCC = 2.7 to 5.5 V) (Normal-ver.) 50 ns (f(BCLK) = 20MHZ, VCC = 4.2 to 5.5 V, -40 to 105°C) (V-ver.) 62.5 ns (f(BCLK) = 16MHZ, VCC = 4.2 to 5.5 V, -40 to 125°C) (V-ver.
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1. Overview M16C/29 Group 1.2 Block Diagram Figure 1.1 is a block diagram of the M16C/29 Group, 80-pin package.
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1. Overview M16C/29 Group Figure 1.2 is a block diagram of the M16C/29 Group, 64-pin package. 4 I/O Ports Port P0 3 8 Port P1 Port P2 4 Port P3 A0 A1 FB ROM(1) USP ISP RAM(2) INTB PC FLG Multiplier NOTES: 1. The ROM capacity varies depending on each product. 2. The RAM capacity varies depending on each product. Figure 1.2 M16C/29 Group, 64-Pin Block Diagram Rev. 1.12 Mar.
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1. Overview M16C/29 Group 1.3 Product List Tables 1.3 to 1.5 list the M16C/29 Group products and Figure 1.3 shows the type numbers, memory sizes and packages. Tables 1.6 to 1.8 list the product code of flash memory version for M16C/29 Group. Figure 1.4 to Figure 1.6 show the marking diagram of flash memory version for M16C/29 Group. Table 1.
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1. Overview M16C/29 Group Table 1.5 Product List (3) -V Version As of March, 2007 ROM Capacity RAM Capacity M30290FAVHP 96 K + 4 K 8K M30290FCVHP 128 K + 4 K 12 K M30291FAVHP 96 K + 4 K 8K M30291FCVHP 128 K + 4 K 12 K M30290M8V-XXXHP 64 K 4K M30290MAV-XXXHP 96 K 8K M30290MCV-XXXHP 128 K 12 K M30291M8V-XXXHP 64 K 4K M30291MAV-XXXHP 96 K 8K M30291MCV-XXXHP 128 K 12 K Type Number Rev. 1.12 Mar.
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1. Overview M16C/29 Group Type No. M 3 0 2 9 0 F A T H P - U3 Product Code See Tables 1.6 and 1.9 for Normal-ver., Tables 1.7 and 1.10 for T-ver., and Tables 1.8 and 1.11 for V-ver.. Package type: HP = Package PLQP0080KB-A (80P6Q-A) Package PLQP0064KB-A (64P6Q-A) Version Blank: Normal-version T: T-version V: V-version ROM capacity /RAM capacity: 8: (64 K) bytes/4 K bytes A: (96 K+4 K) bytes(1)/8 K bytes C: (128 K+4 K) bytes(1)/12 K bytes NOTE: 1. "+4 K bytes" is needed only in flash memory version.
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1. Overview M16C/29 Group Table 1.6 Product Codes of Flash Memory Version Product Code Internal ROM (User Program Space: Blocks 0 to 5) Package Program and Erase Endurance U3 Temperature Range 100 U5 Lead-free U7 10,000 Table 1.
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1. Overview M16C/29 Group (1) Flash Memory Version, PLQP0080KB-A (80P6Q-A), Normal-ver. M16C M30290FAHP A U3 XXXXXXX Product Name: indicates M30290FAHP Chip Version and Product Code: A: indicates chip version The first edition is shown to be blank and continues with A and B. U3: indicates product code (see Table 1.6) Date Code (7 digits): indicates manufacturing management code (2) Flash Memory Version, PLQP0064KB-A (64P6Q-A), Normal-ver.
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1. Overview M16C/29 Group (1) Flash Memory Version, PLQP0080KB-A (80P6Q-A), V-ver. M16C M30290FAVHP A U3 XXXXXXX Product Name: indicates M30290FAVHP Chip Version and Product Code: A: indicates chip version The first edition is shown to be blank and continues with A and B. U3: indicates product code (see Table 1.8) Date Code (7 digits): indicates manufacturing management code (2) Flash Memory Version, PLQP0064KB-A (64P6Q-A), V-ver.
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1. Overview M16C/29 Group 1.4 Pin Assignments P61/CLK0 P62/RxD0 P60/CTS0/RTS0 P25/OUTC15/INPC15 P26/OUTC16/INPC16 P27/OUTC17/INPC17 P24/OUTC14/INPC14 P23/OUTC13/INPC13 P22/OUTC12/INPC12 P21/OUTC11/INPC11/SCLMM P17/INT5/INPC17/IDU P20/OUTC10/INPC10/SDAMM P14 P15/INT3/ADTRG/IDV P16/INT4/IDW P12/AN22 P13/AN23 P07/AN07 P10/AN20 P11/AN21 Figures 1.7 and 1.8 show the pin assignments (top view).
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1. Overview M16C/29 Group Table 1.12 Pin Characteristics for 80-Pin Package Pin No.
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1. Overview M16C/29 Group Table 1.12 Pin Characteristics for 80-Pin Package (continued) Pin No.
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1.
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1. Overview M16C/29 Group Table 1.13 Pin Characteristics for 64-Pin Package Pin No.
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1. Overview M16C/29 Group Table 1.13 Pin Characteristics for 64-Pin Package (continued) Pin No.
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1. Overview M16C/29 Group 1.5 Pin Description Table 1.14 Pin Description (64-pin and 80-pin packages) Classification Symbol Power supply VCC, VSS I/O Type Function Apply 0V to the Vss pin. Apply following voltage to the Vcc pin. I 2.7 to 5.5 V (Normal), 3.0 to 5.5 V (T-ver.), 4.2 to 5.5 V (V-ver.) Supplies power to the A/D converter.
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1. Overview M16C/29 Group Table 1.
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1. Overview M16C/29 Group Table 1.14 Pin Description (80-pin packages only) (Continued) Classification Serial I/O Symbol CLK4 SIN4 I/O Type I/O SOUT4 A/D Converter AN04 to AN07 I O I Function Inputs and outputs the transfer clock Inputs serial data Outputs serial data Analog input pins for the A/D converter AN20 to AN23 AN25 to AN27 I/O Ports P04 to P07 P10 to P14 I/O P34 to P37 P95 to P97 I : Input O : Output Rev. 1.12 Mar.
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2. Central Processing Unit (CPU) M16C/29 Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
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2. Central Processing Unit (CPU) M16C/29 Group 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.
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3. Memory M16C/29 Group 3. Memory Figure 3.1 is a memory map of the M16C/29 Group. M16C/29 Group provides 1-Mbyte address space from addresses 0000016 to FFFFF16. The internal ROM is allocated lower addresses beginning with address FFFFF16. For example, 64-Kbytes internal ROM is allocated addresses F000016 to FFFFF16. Two 2-Kbyte internal ROM areas, block A and block B, are available in the flash memory version. The blocks are allocated addresses F00016 to FFFF16.
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4. Special Function Registers (SFRs) M16C/29 Group 4. Special Function Registers (SFRs) SFRs (Special Function Registers) are the control registers of peripheral functions. Table 4.1 to 4.11 list the SFR address map. Table 4.
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4. Special Function Registers (SFRs) M16C/29 Group Table 4.
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4. Special Function Registers (SFRs) M16C/29 Group Table 4.
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4. Special Function Registers (SFRs) M16C/29 Group Table 4.
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4. Special Function Registers (SFRs) M16C/29 Group Table 4.
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4. Special Function Registers (SFRs) M16C/29 Group Table 4.
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4. Special Function Registers (SFRs) M16C/29 Group Table 4.
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4. Special Function Registers (SFRs) M16C/29 Group Table 4.
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4. Special Function Registers (SFRs) M16C/29 Group Table 4.
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4. Special Function Registers (SFRs) M16C/29 Group Table 4.
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4. Special Function Registers (SFRs) M16C/29 Group Table 4.
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5. Resets M16C/29 Group 5. Resets Hardware reset 1, brown-out detection reset (hardware reset 2), software reset, watchdog timer reset, and oscillation stop detection reset are implemented to reset the MCU. 5.1 Hardware Reset Hardware reset 1 and brown-out detection reset are available as the hardware reset. 5.1.1 Hardware Reset 1 ____________ Pins, CPU, and SFRs are reset by using the RESET pin.
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5. Resets M16C/29 Group Recommended operating voltage VCC 0V RESET VCC RESET 0V Equal to or less than 0.2VCC Equal to or less than 0.2VCC More than td(ROC) + td(P-R) Figure 5.1 Example Reset Circuit 5.2 Software Reset The MCU resets its pins, CPU, and SFRs when the PM03 bit in the PM0 register is set to 1 (reset) and the MCU executes a program in an address indicated by the reset vector. Then the on-chip oscillator is selected as the CPU clock.
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5. Resets M16C/29 Group VCC ROC More than td(ROC) td(P-R) RESET Max. 2 ms CPU clock: 28 cycles CPU clock FFFFC 16 Content of reset vector FFFFE16 Address Figure 5.2 Reset Sequence ____________ Table 5.
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5. Resets M16C/29 Group 5.5 Voltage Detection Circuit Note VCC = 5 V is assumed in 5.5 Voltage Detection Circuit. Voltage detection circuit in the M16C/29 Group, T-ver. and V-ver. cannot be used. The voltage detection circuit has the reset level detection circuit and the low voltage detection circuit. The reset level detection circuit monitors the voltage applied to the VCC pin. The MCU is reset if the reset level detection circuit detects VCC is Vdet3 or below.
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5. Resets M16C/29 Group Voltage Detection Register 1 b7 b6 b5 b4 0 0 0 0 b3 b2 b1 b0 0 0 0 Symbol VCR1 Address 001916 Bit Symbol (b2-b0) VC13 (b7-b4) After Reset (2) 000010002 Function Bit Name RW Reserved bit Set to 0 RW Low voltage monitor flag (1) 0:VCC < Vdet4 1:VCC ≥ Vdet4 RO Reserved bit Set to 0 RW NOTES: 1. The VC13 bit is useful when the VC27 bit of VCR2 register is set to 1 (low voltage detection circuit enable).
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5.
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5. Resets M16C/29 Group 5.5.1 Low Voltage Detection Interrupt If the D40 bit in the D4INT register is set to 1 (low voltge detection interrupt enabled), a low voltage detection interrupt request is generated when voltage applied to the VCC pin is above or below Vdet4. The low voltage detection interrupt shares the same interrupt vector with watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
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5. Resets M16C/29 Group Low voltage detection interrupt generation circuit DF1, DF0 002 D42 bit is set to 0 (not detected) by writing a 0 in a program. VC27 bit is 012 Low voltage detection circuit 102 D4INT clock(the clock with which it operates also in wait mode) VC27 1/8 1/2 1/2 1/2 set to 0 (low voltage detection circuit disabled), the D42 bit is set to 0.
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5. Resets M16C/29 Group 5.5.2. Limitations on Stop Mode When all the conditions below are met, the low voltage detection interrupt is generated and the MCU exits stop mode as soon as the CM10 bit in the CM1 register is set to 1 (all clocks stopped).
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6. Processor Mode M16C/29 Group 6. Processor Mode The MCU supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers. Processor Mode Register 0 (1) b7 b6 b5 b4 b3 0 0 0 0 b2 b1 b0 0 0 0 Symbol PM0 Address 000416 Bit Symbol After Reset 0016 Bit Name Function RW (b2-b0) Reserved bit Set to 0 RW PM03 Software reset bit The MCU is reset when this bit is set to 1. When read, its content is 0. RW (b7-b4) Reserved bit Set to 0 RW NOTES: 1.
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6.
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6. Processor Mode M16C/29 Group The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and peripheral bus. Figure 6.3 shows the block diagram of the internal bus. ROM RAM CPU address bus CPU CPU data bus Memory address bus BIU Memory data bus DMAC Timer WDT ADC CAN CRC . .
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7. Clock Generation Circuit M16C/29 Group 7. Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit (3) Variable on-chip oscillators (4) PLL frequency synthesizer Table 7.1 lists the specifications of the clock generation circuit. Figure 7.1 shows the clock generation circuit. Figures 7.2 to 7.7 show clock-associated registers. Table 7.
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7.
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7. Clock Generation Circuit M16C/29 Group System Clock Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Address 000616 Bit Symbol CM00 After Reset 010010002 Bit Name Clock output function select bit Function See Table 7.
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7.
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7.
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7.
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7. Clock Generation Circuit M16C/29 Group PLL Control Register 0 b7 b6 b5 b4 b3 b2 b1 (1,2) Symbol PLC0 b0 0 0 1 Bit Symbol PLC00 Address 001C16 After Reset 0001X0102 Bit Name PLL multiplying factor (3) select bit PLC01 PLC02 Function b2 b1b0 0 0 0: Do not set 0 0 1: Multiply by 2 0 1 0: Multiply by 4 0 1 1: 1 0 0: 1 0 1: Do not set 1 1 0: 1 1 1: RW RW RW RW (b3) Nothing is assigned. If necessary, set to 0.
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7. Clock Generation Circuit M16C/29 Group The following describes the clocks generated by the clock generation circuit. 7.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins.
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7. Clock Generation Circuit M16C/29 Group 7.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT pins.
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7. Clock Generation Circuit M16C/29 Group 7.3 On-chip Oscillator Clock This clock is supplied by a variable on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is 1 (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to 10. Watchdog Timer • Count source protective mode”).
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7. Clock Generation Circuit M16C/29 Group START Set the CM07 bit to 0 (main clock), bits CM17 and CM16 to 002(main clock undivided), and the CM06 bit to 0 (bits CM17 and CM16 enabled). (1) Set bits PLC02 to PLC00 (multiplying factor). (To select a 16 MHz or higher PLL clock) Set the PM20 bit to 0 (2-wait states). Set the PLC07 bit to 1 (PLL operation). Wait until the PLL clock becomes stable (tsu(PLL)). Set the CM11 bit to 1 (PLL clock for the CPU clock source). END NOTE: 1.
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7. Clock Generation Circuit M16C/29 Group 7.5 CPU Clock and Peripheral Function Clock The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the peripheral functions. 7.5.1 CPU Clock This is the operating clock for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the PLL clock.
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7. Clock Generation Circuit M16C/29 Group 7.6 Power Control There are three power control modes. In this chapter, all modes other than wait and stop modes are referred to as normal operation mode. 7.6.1 Normal Operation Mode Normal operation mode is further classified into seven modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency.
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7. Clock Generation Circuit M16C/29 Group 7.6.1.6 On-chip Oscillator Mode The selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for timers A and B. The on-chip oscillator frequency can be selected by bits ROCR3 to ROCR0 in the ROCR register.
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7. Clock Generation Circuit M16C/29 Group 7.6.2.3 Pin Status During Wait Mode Table 7.5 lists pin status during wait mode. Table 7.5 Pin Status in Wait Mode Pin Status I/O ports When fC selected CLKOUT When f1, f8, f32 selected Retains status before wait mode Does not stop Does not stop when the CM02 bit is set to 0 Retains status before wait mode when the CM02 bit is set to 1 7.6.2.
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7. Clock Generation Circuit M16C/29 Group 7.6.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the internal RAM is retained. When applying 2.7 or less voltage to Vcc pin, make sure Vcc≥VRAM.
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7. Clock Generation Circuit M16C/29 Group Figure 7.11 shows the state transition from normal operation mode to stop mode and wait mode. Figure 7.12 shows the state transition in normal operation mode. Table 7.7 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line shows state after transition.
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7.
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7. Clock Generation Circuit M16C/29 Group Table 7.
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7. Clock Generation Circuit M16C/29 Group 7.7 System Clock Protective Function When the main clock is selected for the CPU clock source, this function protects the clock from modifications in order to prevent the CPU clock from becoming halted by run-away.
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7. Clock Generation Circuit M16C/29 Group 7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) When main clock stop is detected when the CM20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the MCU is initialized, coming to a halt (oscillation stop reset; refer to “SFR”, “Reset”). This status is reset with hardware reset 1. Also, even when re-oscillation is detected, the MCU can be initialized and stopped; it is, however, necessary to avoid such usage.
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7. Clock Generation Circuit M16C/29 Group 7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer interrupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
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8. Protection M16C/29 Group 8. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
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9. Interrupts M16C/29 Group 9. Interrupts Note The SI/O4 interrupt of peripheral function interrupts is not available in the 64-pin package. The low voltage detection function is not available in M16C/29 T-ver. and V-ver.. 9.1 Type of Interrupts Figure 9.1 shows types of interrupts.
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9. Interrupts M16C/29 Group 9.1.1 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 9.1.1.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 9.1.1.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to 1 (the operation resulted in an overflow).
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9. Interrupts M16C/29 Group 9.1.2 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 9.1.2.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details _______ about the NMI interrupt, refer to the section "NMI interrupt". ________ 9.1.2.1.
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9. Interrupts M16C/29 Group 9.2 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 9.2 shows the interrupt vector. MSB Vector address (L) LSB Low address Mid address Vector address (H) 0000 High address 0000 0000 Figure 9.2 Interrupt Vector 9.2.
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9. Interrupts M16C/29 Group 9.2.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 9.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses. Table 9.
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9. Interrupts M16C/29 Group 9.3 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use I flag in the the FLG register, IPL, and bits ILVL2 to ILVL0 in the each interrupt control register to enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 9.
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9.
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9. Interrupts M16C/29 Group 9.3.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (= enabled) enables the maskable interrupt. Setting the I flag to 0 (= disabled) disables all maskable interrupts. 9.3.2 IR Bit The IR bit is set to 1 (= interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to 0 (= interrupt not requested).
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9. Interrupts M16C/29 Group 9.4 Interrupt Sequence An interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the interrupt routine is executed) is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
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9. Interrupts M16C/29 Group 9.4.1 Interrupt Response Time Figure 9.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is generated till when the instruction then executing is completed ((a) in Figure 9.
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9. Interrupts M16C/29 Group 9.4.3 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 9.7 shows the stack status before and after an interrupt request is accepted.
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9. Interrupts M16C/29 Group The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP(1), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (1) is even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 9.8 shows the operation of the saving registers. NOTE: 1.
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9. Interrupts M16C/29 Group 9.4.4 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
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9. Interrupts M16C/29 Group ______ 9.6 INT Interrupt _______ INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. ________ The INT5 input has an effective digital debounce function for a noise rejection. Refer to "19.6 Digital ________ Debounce function" for this detail. When using INT5 interrupt to exit stop mode, set the P17DDR register to FF16 before entering stop mode.
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9. Interrupts M16C/29 Group ______ 9.7 NMI Interrupt _______ _______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the _______ ______ NMI interrupt was enabled by writing a 1 to bit 4 in the register PM2. The NMI interrupt is a non-maskable interrupt, once it is enabled. _______ The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register.
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9. Interrupts M16C/29 Group 9.9 CAN0 Wake-up Interrupt CAN0 wake-up interrupt occurs when a falling edge is input to CRX. The CAN0 wake-up interrupt is enabled when the PortEn bit is set to 1 (CTX/CRX function) and Sleep bit is set to 1(Sleep mode enabled) in the C0CTLR register. Figure 9.13 shows the block diagram of the CAN0 wake-up interrupt. C01WKIC register Sleep bit in C0CTLR register PortEn bit in C0CTLR register Interrupt control circuit CRX CAN0 wake-up interrupt request Figure 9.
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9. Interrupts M16C/29 Group Table 9.6 PC Value Saved in Stack Area When Address Match Interrupt Request Is Acknowledged Value of the PC that is saved to the stack area Instruction at the address indicated by the RMADi register • 2-byte op-code instruction • 1-byte op-code instructions which are followed: ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B #IMM8,dest STNZ.B #IMM8,dest STZX.B #IMM81,#IMM82,dest CMP.
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10. Watchdog Timer M16C/29 Group 10. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.
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11. DMAC M16C/29 Group 11. DMAC Note Do not use SI/O4 interrupt request as a DMA request in the 64-pin package. The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address. The DMAC uses the same data bus as used by the CPU.
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11. DMAC M16C/29 Group Table 11.1 DMAC Specifications Item No. of channels Transfer memory space Maximum No.
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11. DMAC M16C/29 Group DMA0 Request Cause Select Register b7 b6 b5 b4 b3 b2 b1 Symbol DM0SL b0 Bit Symbol Address 03B816 Bit Name After Reset 0016 Function DSEL0 DSEL1 DSEL2 RW DMA request cause select bit Refer to note (1) RW RW DSEL3 (b5-b4) RW RW Nothing is assigned. When write, set to 0.
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11. DMAC M16C/29 Group DMA1 Request Cause Select Register b7 b6 b5 b4 b3 b2 b1 Symbol DM1SL b0 Address 03BA16 DSEL1 DSEL2 Function Bit Name Bit Symbol DSEL0 After Reset 0016 DMA request cause select bit Refer to note (1) RW RW RW RW DSEL3 RW (b5-b4) Nothing is assigned. If necessary, set to 0.
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11. DMAC M16C/29 Group DMAi Source Pointer (i = 0, 1) (1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 Symbol SAR0 SAR1 b0 Address 002216 to 0020 16 003216 to 0030 16 Function Set the source address of transfer After Reset Undefined Undefined Setting Range RW 00000 16 to FFFFF 16 RW Nothing is assigned. If necessary, set 0. When read, the contents are 0 NOTE: 1.
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11. DMAC M16C/29 Group 11.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer. Furthermore, the bus cycle itself is extended by a software wait. 11.1.
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11. DMAC M16C/29 Group (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address CPU clock Address bus CPU use Dummy cycle Destination Source CPU use RD signal WR signal Data bus CPU use Dummy cycle Destination Source CPU use (2) When the transfer unit is 16 bits and the source address of transfer is an odd address.
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11. DMAC M16C/29 Group 11.2. DMA Transfer Cycles Any combination of even or odd transfer read and write adresses is possible. Table 11.2 shows the number of DMA transfer cycles. Table 11.3 shows the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 11.
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11. DMAC M16C/29 Group 11.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to 1 (enabled), the DMAC operates as follows: (a) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register is 1 (forward) or the DARi register value when the DAD bit in the DMiCON register is 1 (forward). (b) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
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11. DMAC M16C/29 Group 11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of CPU clock), the DMAS bit on each channel is set to 1 (DMA requested) at the same time. In this case, the DMA requests are arbitrated according to the channel priority, DMA0 > DMA1.
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12. Timers M16C/29 Group 12. Timers Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (three). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. Figures 12.1 and 12.2 show block diagrams of timer A and timer B configuration, respectively.
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12.
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12. Timer A M16C/29 Group 12.1 Timer A Figure 12.3 shows a block diagram of the timer A. Figures 12.4 to 12.6 show registers related to the timer A. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function. Use bits TMOD1 to TMOD0 in the TAiMR register (i = 0 to 4) to select the desired mode. • Timer mode: The timer counts an internal count source.
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12.
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12. Timer A M16C/29 Group One-shot Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Bit Symbol Address 038216 Function RW The timer starts counting by setting this bit to 1 while bits TMOD1 and TMOD0 in the TAiMR register (i = 0 to 4) = 10 2 (= one-shot timer mode) and the MR2 bit in the TAiMR register = 0 (=TAiOS bit enabled).
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12. Timer A M16C/29 Group 12.1.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.1). Figure 12.7 shows TAiMR register in timer mode. Table 12.
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12. Timer A M16C/29 Group 12.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3, and A4 can count two-phase external signals. Table 12.2 lists specifications in event counter mode (when not processing two-phase pulse signal). Table 12.3 lists specifications in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4). Figure 12.
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12. Timer A M16C/29 Group Table 12.
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12. Timer A M16C/29 Group 12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to 0 by Z-phase (counter initialization) input during twophase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal process_______ ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
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12. Timer A M16C/29 Group 12.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.4) When the trigger occurs, the timer starts up and continues operating for a given period. Figure 12.11 shows the TAiMR register in one-shot timer mode. Table 12.
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12.
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12. Timer A M16C/29 Group 12.1.4 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.12 shows TAiMR register in pulse width modulation mode. Figures 12.13 and 12.14 show examples of how a 16bit pulse width modulator operates and how an 8-bit pulse width modulator operates. Table 12.
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12.
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12. Timer A M16C/29 Group 1 / f i X (2 16 – 1) Count source Input signal to TAiIN pin “H” PWM pulse output from TA iOUT pin “H” “L” Trigger is not generated by this signal 1 / fj X n “L” 1 IR bit in the TAiIC register 0 fj : Frequency of count source (f1, f 2, f8, f 32, fC32) i = 0 to 4 Set to 0 upon accepting an interrupt request or by program NOTES: 1. n = 0000 16 to FFFE 16. 2.
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12. Timer B M16C/29 Group 12.2 Timer B Figure 12.15 shows a block diagram of the timer B. Figures 12.16 and 12.17 show registers related to the timer B. Timer B supports the following four modes. Use bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 2) to select the desired mode. • Timer mode: The timer counts the internal count source. • Event counter mode: The timer counts the external pulses or overflows and underflows of other timers.
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12.
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12. Timer B M16C/29 Group 12.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.6). Figure 12.18 shows TBiMR register in timer mode. Table 12.
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12. Timer B M16C/29 Group 12.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 12.7). Figure 12.19 shows the TBiMR register in event counter mode. Table 12.
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12. Timer B M16C/29 Group 12.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 12.8). Figure 12.20 shows the TBiMR register in pulse period and pulse width measurement mode. Figure 12.21 shows the operation timing when measuring a pulse period. Figure 12.22 shows the operation timing when measuring a pulse width. Table 12.
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12. Timer B M16C/29 Group Count source “H” Measurement pulse Reload register transfer timing “L” Transfer (undefined value) Transfer (measured value) counter (1) (1) (2) Timing at which counter reaches 000016 1 TBiS bit 0 TBiIC register's IR bit 1 TBiMR register's MR3 bit 1 0 Set to 0 upon accepting an interrupt request or by program 0 Bits TB0S to TB2S are assigned to the bit 5 to bit 7 in the TABSR register. i = 0 to 2 NOTES: 1. Counter is initialized at completion of measurement. 2.
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12. Timer B M16C/29 Group 12.2.4 A/D Trigger Mode A/D trigger mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A/D conversion to start A/D conversion. It is used in timer B0 and timer B1 only. In this mode, the timer starts counting by one trigger until the count value becomes 000016. Figure 12.23 shows the TBiMR register in A/D trigger mode and Figure 12.24 shows the TB2SC register. Table 12.
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12. Timer B M16C/29 Group AA A AA A Timer Bi Mode Register (i= 0 to 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol TB0MR to TB1MR Bit Symbol TMOD0 Address 039B16 to 039C16 Function Bit Name Operation mode select bit TMOD1 MR0 After Reset 00XX00002 b1 b0 0 0: Timer mode or A/D trigger mode Invalid in A/D trigger mode Either 0 or 1 is enabled MR1 RW RW RW TB0MR register Set to 0 in A/D trigger mode MR2 RW RW RW TB1MR register Nothing is assigned. If necessary, set to 0.
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12. Timer (Three-phase Motor Control Timer Function) M16C/29 Group 12.3 Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.10 lists the specifications of the three-phase motor control timer function. Figure 12.24 shows the block diagram for three-phase motor control timer function. Also, the related registers are shown on Figures 12.26 to 12.32. Table 12.
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Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 126 of 458 T Q INV11 (One-shot timer mode) Timer A4 counter Reload TA41 register Figure 12.
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12. Timer (Three-phase Motor Control Timer Function) M16C/29 Group Three-phase Output Buffer Register(i=0,1) (1) b7 b4 b3 b2 b1 b0 0 Symbol Address After Reset IDB0 034A16 001111112 034B16 001111112 IDB1 Bit Symbol Bit Name Function RW DUi U phase output buffer i DUBi U phase output buffer i Write the output level 0: Active level 1: Inactive level DVi V phase output buffer i When read, these bits show the three-phase output shift register value.
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12. Timer (Three-phase Motor Control Timer Function) M16C/29 Group Timer Ai, Ai-1 Register (i=1, 2, 4) (1, 2, 3, 4, 5) (b15) b7 (b8) b0 b7 b0 Symbol TA1 TA2 TA4 TA11(6,7) TA21(6,7) TA41(6,7) Address 038916-038816 038B16-038A16 038F16-038E16 034316-034216 034516-034416 034716-034616 Function Assuming the set value = n, upon a start trigger the timer starts counting the count source and stops after counting it n times. The positive and negative phases change at the same time timer A, A2 or A4 stops.
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12. Timer (Three-phase Motor Control Timer Function) M16C/29 Group Timer B2 Register (1) (b15) b7 (b8) b0 b7 b0 Symbol TB2 Address 039516-039416 After Reset Undefined Setting Range Function Divide the count source by n + 1 where n = set value. Timer A1, A2 and A4 are started at every occurrence of underflow. 000016 to FFFF16 RW RW NOTE: 1. Access the register by 16 bit units.
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12. Timer (Three-phase Motor Control Timer Function) M16C/29 Group The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to 1. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to __ ___ ___ control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated deadtime timer. Figure 12.33 shows the example of triangular modulation waveform, and Figure 12.
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12. Timer (Three-phase Motor Control Timer Function) M16C/29 Group Sawtooth Waveform as a Carrier Wave Sawtooth wave Signal wave Timer B2 Start trigger signal for timer A4(1) Timer A4 one-shot pulse(1) Rewrite registers IDB0 and IDB1 Transfer the values to the threephase output shift register U phase output signal (1) U phase output signal (1) INV14 = 0 (“L” active) U phase Dead time U phase INV14 = 1 (“H” active) U phase Dead time U phase NOTE: 1. Internal signals. See Figure 12.25.
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12. Timer (Three-phase Motor Control Timer Function) M16C/29 Group 12.3.1 Position-Data-Retain Function This function is used to retain the position data synchronously with the three-phase waveform output.There are three position-data input pins for U, V, and W phases. A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected by the PDRT bit in the PDRF register.
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12. Timer (Three-phase Motor Control Timer Function) M16C/29 Group 12.3.1.2 Position-data-retain Function Control Register Figure 12.36 shows the structure of the position-data-retain function contol register.
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12. Timer (Three-phase Motor Control Timer Function) M16C/29 Group 12.3.2 Three-phase/Port Output Switch Function When the INVC03 bit in the INVC0 register set to 1 (Timer output enabled for three-phase motor control) __ and setting the PFCi (i=0 to 5) in the PFCR register to 0 (I/O port), the three-phase PWM output pin (U, U, __ ___ V, V, W and W) functions as I/O port. Each bit of the PFCi bits (i=0 to 5) is applicable for each one of three-phase PWM output pins. Figure 12.
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12.
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13. Timer S M16C/29 Group 13. Timer S The Timer S (Input Capture/Output Compare : here after, Timer S is referred to as "IC/OC".) is a highperformance I/O port for time measurement and waveform generation. The IC/OC has one 16-bit base timer for free-running operation and eight 16-bit registers for time measurement and waveform generation. Table 13.1 lists functions and channels of the IC/OC. Table 13.
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13. Timer S M16C/29 Group Figure 13.1 shows the block diagram of the IC/OC.
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13. Timer S M16C/29 Group Figures 13.2 to 13.10 show registers associated with the IC/OC base timer, the time measurement function, and the waveform generating function. Base Timer Register b15 (b7) b8 (b0) b7 b0 (1) Symbol G1BT Address 032116 - 032016 After Reset Undefined Setting Range Function When the base timer is operating: When read, the value of base timer plus 1 can be read. When write, the counter starts counting from the value written.
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13. Timer S M16C/29 Group Divider Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1DV Address 032A16 Function After Reset 0016 Setting range Divide f1, f2 or two-phase pulse input by (n+1) for fBT1 clock cycles generation.
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13. Timer S M16C/29 Group Base Timer Reset Register(1) b15 (b7) b8 (b0) b7 Symbol G1BTRR b0 Address 032916 - 032816 Function When enabled by the RST4 bit in the G1BCR0 register, the base timer is reset by matching the G1BTRR register setting value and the base timer setting value. After Reset Undefined Setting Range RW 000016 to FFFF16 RW NOTE: 1. The G1BTRR register reflects the value of the base timer, synchronizing with the count source fBT1 cycles. Figure 13.4 G1BTRR Register Rev. 1.
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13.
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13. Timer S M16C/29 Group Waveform Generation Register j (j=0 to 7) b15 (b7) b8 (b0) b7 b0 Symbol G1PO0 to G1PO2 G1PO3 to G1PO5 G1PO6 to G1PO7 Address 030116-030016, 030316-030216, 030516-030416 030716-030616, 030916-030816, 030B16-030A16 030D16-030C16, 030F16-030E16 Function When the RLD bit in the G1POCRj register is set to 0, value written is immediately reloaded into the G1POj register for output, for example, a waveform output,reflecting the value.
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13. Timer S M16C/29 Group Interrupt Request Register b7 b6 b5 b4 b3 b2 b1 b0 (1) Symbol Address After Reset G1IR 033016 Undefined Bit Symbol Bit Name G1IR0 Interrupt request, Ch0 G1IR1 Interrupt request, Ch1 RW G1IR2 Interrupt request, Ch2 RW G1IR3 Interrupt request, Ch3 RW G1IR4 Interrupt request, Ch4 RW G1IR5 Interrupt request, Ch5 RW G1IR6 Interrupt request, Ch6 RW G1IR7 Interrupt request, Ch7 RW Function 0 : No interrupt request 1 : Interrupt requested NOTE: 1.
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13. Timer S M16C/29 Group 13.1 Base Timer The base timer is a free-running counter that counts an internally generated count source. Table 13.2 lists specifications of the base timer. Table 13.3 shows registers associated with the base timer. Figure 13.11 shows a block diagram of the base timer. Figure 13.12 shows an example of the base timer in counter increment mode. Figure 13.13 shows an example of the base timer in counter increment/decrement mode. Figure 13.
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13. Timer S M16C/29 Group fBT1 f1 or f2 Two-phase pulse input 11 BCK1 to BCK0 (n+1) divider 10 Base timer b14 b15 (Note 1) Overflow signal Base timer overflow request 0 BTS bit in G1BCR1 register 1 RST4 IT Matched with G1BTRR RST1 Matched with G1PO0 register RST2 Input "L" to INT1 pin Base timer reset NOTE: 1. Divider is reset when the BTS bit is set to 0. IT, RST4, BCK1 to BCK0: Bits in the G1BCR0 register RST2 to RST1: Bits in the G1BCR1 register Figure 13.
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13. Timer S M16C/29 Group FFFF16 C00016 State of a counter 800016 400016 000016 IT=1 in the G1BCR0 register (Base timer interrupt generated by the bit 14 overflow) b14 overflow signal 1 0 Base Timer interrupts IT=0 in the G1BCR0 register (Base timer interrupt generated by the bit 15 overflow) b15 overflow signal 1 0 Base Timer interrupt The above applies to the following conditions.
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13. Timer S M16C/29 Group 13.1.1 Base Timer Reset Register(G1BTRR) The G1BTRR register provides the capability to reset the base timer when the base timer count value matches the value stored in the G1BTRR register. The G1BTRR register is enabled by the RST4 bit in the G1BCR0 register. This function is identical in operation to the G1PO0 base timer reset that is enabled by the RST1 bit in the G1BCR0 reigster.
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13. Timer S M16C/29 Group 13.2 Interrupt Operation The IC/OC interrupt contains several request causes. Figure 13.18 shows the IC/OC interrupt block diagram and Table 13.4 shows the IC/OC interrupt assignation. When either the base timer reset request or base timer overflow request is generated, the IR bit in the BTIC register corresponding to the IC/OC base timer interrupt is set to 1 (with an interrupt request).
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13. Timer S M16C/29 Group 13.4 Time Measurement Function In synchronization with an external trigger input, the value of the base timer is stored into the G1TMj register (j=0 to 7). Table 13.5 shows specifications of the time measurement function. Table 13.6 shows register settings associated with the time measurement function. Figures 13.19 and 13.20 display operational timing of the time measurement function. Figure 13.21 shows operational timing of the prescaler function and the gate function.
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13. Timer S M16C/29 Group Table 13.
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13. Timer S M16C/29 Group (a) When selecting the rising edge as a timer measurement trigger (Bits CTS1 and CTS0 in the G1TMCRj register (j=0 to 7)=012) fBT1 Base timer n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 (2) INPC1j pin input or trigger signal after passing the digital filter G1IRj bit (1) write 0 by program if setting to 0 Delayed by 1 clock G1TMj register n n +5 n+8 NOTES : 1. Bits in the G1IR register. 2.
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13. Timer S M16C/29 Group (a) With the prescaler function (When the G1TPRj register (j = 6, 7) is set to 0216, the PR bit in the G1TMCRj register (j = 6, 7) is set to 1) fBT1 Base timer n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 +12 n+13 n+14 INPC1j pin input or trigger signal after passing the digital filter Internal time measurement trigger 2 Prescaler (1) 2 0 1 Set 0 by program if necessary G1IRj bit (2) G1TMj register n+1 n+13 NOTES: 1.
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13. Timer S M16C/29 Group 13.5 Waveform Generating Function Waveforms are generated when the base timer value matches the G1POj (j=0 to 7) register value. The waveform generating function has the following three modes : • Single-phase waveform output mode • Phase-delayed waveform output mode • Set/Reset waveform output (SR waveform output) mode Table 13.7 lists registers associated with the waveform generating function. Table 13.
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13. Timer S M16C/29 Group 13.5.1 Single-Phase Waveform Output Mode Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRj (j=0 to 7) register is set to 0(output is not reversed) and the base timer value matches the G1POj (j=0 to 7) register value. The "H" signal switches to a low-level ("L") signal when the base timer reaches 000016. Table 13.8 lists specifications of single-phase waveform mode. Figure 13.22 lists an example of single-phase waveform mode operation.
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13. Timer S M16C/29 Group (1) Free-running operation (The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to 0) FFFF16 Base timer m 000016 m fBT1 65536-m fBT1 Inverse OUTC1j pin 65536 fBT1 G1IRj bit Inverse Return to default output level When setting to 0, write 0 by program j=0 to 7 m : Setting value of the G1POj register G1IRj bit : Bits in the G1IR register The above applies under the following conditions.
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13. Timer S M16C/29 Group 13.5.2 Phase-Delayed Waveform Output Mode Output signal level of the OUTC1j pin is inversed every time the base timer value matches the G1POj register value ( j=0 to 7). Table 13.9 lists specifications of phase-delayed waveform mode. Figure 13.23 shows an example of phase-delayed waveform mode operation. Table 13.
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13. Timer S M16C/29 Group (1) Free-running operation (Bits RST4, RST2, and RST1 in the registers G1BCR0 and G1BCR1 are set to 0) FFFF16 Base timer m 000016 65536 fBT1 65536 fBT1 OUTC1j pin Inverse Inverse 65536X2 fBT1 Write 0 by program if setting to 0 G1IRj bit j=0 to 7 m : Setting value of the G1POj register G1IRj bit : Bits in the G1IR register The above applies under the following conditions. The IVL bit in the G1POCRj register is set to 0 (L output as a default value).
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13. Timer S M16C/29 Group 13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRi (i=0 to 7) is set to 0 (output is not reversed) and the base timer value matches the G1POj register value (j=0, 2, 4, 6). The "H" signal switches to a low-level ("L") signal when the base timer value matches the G1POk (k=j+1) register value. Table 13.10 lists specifications of SR waveform mode. Figure 13.
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13.
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13. Timer S M16C/29 Group 13.6 I/O Port Function Select The value in the G1FE and G1FS registers decides which IC/OC pin to be an input or output pin. In SR waveform generating mode, two channels, a set of even channel and odd channel, are used every output waveform, however, the waveform is output from an even channel only. In this case, the corresponding pin to the odd channel can be used as an I/O port. Table 13.
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13. Timer S M16C/29 Group 13.6.1 INPC17 Alternate Input Pin Selection The input capture pin for IC/OC channel 7 can be assigned to one of two package pins. The CH7INSEL ________ bit in the G1BCR0 register selects IC/OC INPC17 from P27/OUTC17/INPC17 or P17/INT5/INPC17/IDU. ________ 13.6.2 Digital Debounce Function for Pin P17/INT5/INPC17 ________ ________ The INT5/INPC17 input from the P17/INT5/INPC17/IDU pin has an effective digital debounce function against a noise rejection. Refer to 19.
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14.Serial I/O M16C/29 Group 14. Serial I/O Note The SI/O4 interrupt of peripheral function interrupt is not available in the 64-pin package. Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4. 14.1 UARTi (i=0 to 2) UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 14.1 shows the block diagram of UARTi. Figures 14.2 and 14.3 shows the block diagram of the UARTi transmit/receive.
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14.
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14.Serial I/O M16C/29 Group UARTi Transmit Buffer Register (i=0 to 2)(1) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A3 16-03A2 16 03AB 16-03AA 16 037B 16-037A 16 After Reset Undefined Undefined Undefined Function RW Transmit data WO Nothing is assigned. If necessary, set to 0. When read, their contents are undefined NOTES: 1. Use MOV instruction to write to this register.
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14.
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14.
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14. Serial I/O M16C/29 Group UART2 Special Mode Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Bit Symbol Address 0375 16 After Reset 000X0X0X 2 Bit Name Function RW Nothing is assigned. If necessary, set to 0. When read, the content is undefined (b0) CKPH Clock phase set bit 0 : Without clock delay 1 : With clock delay RW Nothing is assigned. If necessary, set to 0.
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14.Serial I/O M16C/29 Group 14.1.1 Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1 lists the specifications of the clock synchronous serial I/O mode. Table 14.2 lists the registers used in clock synchronous serial I/O mode and the register values set. Table 14.
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14. Serial I/O M16C/29 Group Table 14.
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14.Serial I/O M16C/29 Group Table 14.3 lists pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 14.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.) Table 14.
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14.
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14.Serial I/O M16C/29 Group 14.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below.
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14. Serial I/O M16C/29 Group 14.1.1.2 CLK Polarity Select Function Use the CKPOL bit in the UiC0 register (i=0 to 2) to select the transfer clock polarity. Figure 14.11 shows the polarity of the transfer clock.
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14.Serial I/O M16C/29 Group 14.1.1.4 Continuous receive mode When the UiRRM bit (i=0 to 2) is set to 1 (continuous receive mode), the TI bit in the UiC1 register is set to 0 (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit is set to 1, do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the bit 2 and bit 3 in the UCON register, respectively, and the U2RRM bit is the bit 5 in the U2C1 register. 14.1.1.
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14. Serial I/O M16C/29 Group _______ _______ 14.1.1.7 CTS/RTS separate function (UART0) _______ _______ _______ _______ This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64 pin or P70 pin. To use this function, set the register bits as shown below.
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14.Serial I/O M16C/29 Group 14.1.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Table 14.5 lists the specifications of the UART mode. Table 14.
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14. Serial I/O M16C/29 Group Table 14.
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14.Serial I/O M16C/29 Group Table 14.7 lists the functions of the input/output pins in UART mode. Table 14.8 lists the P64 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.) Table 14.
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14. Serial I/O M16C/29 Group • Example of transmit timing when transfer data is 8-bit long (parity enabled, one stop bit) The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
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14.
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14. Serial I/O M16C/29 Group 14.1.2.2 Counter Measure for Communication Error If a communication error occurs while transmitting or receiving in UART mode, follow the procedure below.
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14.Serial I/O M16C/29 Group 14.1.2.4 Serial Data Logic Switching Function (UART2) The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the U2RB register. Figure 14.19 shows serial data logic.
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14. Serial I/O M16C/29 Group _______ _______ 14.1.2.6 CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64 pin or P70 pin. To use this function, set the register bits as shown below.
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14. Serial I/O M16C/29 Group 14.1.3 Special Mode 1 (I2C bus mode)(UART2) I2C bus mode is provided for use as a simplifed I2C bus interface compatible mode. Table 14.10 lists the specifications of the I2C bus mode. Tables 14.11 and 14.12 list the registers used in the I2C bus mode and the register values set. Table 14.13 lists the I2C bus mode fuctions. Figure 14.22 shows the block diagram for I2C bus mode. Figure 14.23 shows SCL2 timing. As shown in Table 14.
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14. Serial I/O M16C/29 Group Table 14.
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14. Serial I/O M16C/29 Group Table 14.
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14. Serial I/O M16C/29 Group Table 14.13 I2C bus mode Functions Function Clock synchronous serial I/O I2C bus mode (SMD2 to SMD0 = 0102, IICM = 1) mode (SMD2 to SMD0 = 0012, IICM2 = 0 IICM2 = 1 IICM = 0) (NACK/ACK interrupt) (UART transmit/ receive interrupt) CKPH = 1 CKPH = 1 CKPH = 0 CKPH = 0 (Clock delay) (No clock delay) (Clock delay) (No clock delay) Factor of interrupt number 10 (1) (Refer to Fig.14.23) Start condition detection or stop condition detection (Refer to Table 14.
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14.
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14. Serial I/O M16C/29 Group 14.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDA2 pin changes state from high to low while the SCL2 pin is in the high state. A stop condition-detected interrupt request is generated when the SDA2 pin changes state from low to high while the SCL2 pin is in the high state.
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14. Serial I/O M16C/29 Group Table 14.
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14. Serial I/O M16C/29 Group 14.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 14.25. The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal SCL2) and an external clock supplied to the SCL2 pin.
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14. Serial I/O M16C/29 Group 14.1.3.7 ACK and NACK If the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not generated) and the ACKC bit in the U2SMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the U2SMR4 register is output from the SDA2 pin. If the IICM2 bit is set to 0, a NACK interrupt request is generated if the SDA2 pin remains high at the rising edge of the 9th bit of transmit clock pulse.
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14. Serial I/O M16C/29 Group 14.1.4 Special Mode 2 (UART2) Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 14.15 lists the specifications of Special Mode 2. Table 14.16 lists the registers used in Special Mode 2 and the register values set. Figure 14.26 shows communication control example for Special Mode 2. Table 14.
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14. Serial I/O M16C/29 Group P13 P12 P93 P72(CLK2) P72(CLK2) P71(RxD2) P71(RxD2) P70(TxD2) P70(TxD2) MCU (Master) MCU (Slave) P93 P72(CLK2) P71(RxD2) P70(TxD2) MCU (Slave) Figure 14.26 Serial Bus Communication Control Example (UART2) Table 14.
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14. Serial I/O M16C/29 Group 14.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the U2SMR3 register and the CKPOL bit in the U2C0 register. Make sure the transfer clock polarity and phase are the same for the master and slave to communicate. 14.1.4.1.1 Master (Internal Clock) Figure 14.27 shows the transmission and reception timing in master (internal clock). 14.1.4.1.2 Slave (External Clock) Figure 14.
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14. Serial I/O M16C/29 Group Slave control input "H" "L" "H" Clock input (CKPOL=0, CKPH=0) "L" "H" Clock input (CKPOL=1, CKPH=0) "L" Data output timing "H" D0 "L" Data input timing D1 D2 D3 D4 D5 D6 D7 Undefined Figure 14.
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14. Serial I/O M16C/29 Group 14.1.5 Special Mode 3 (IEBus mode)(UART2) In this mode, one bit in the IEBus is approximated with one byte of UART mode waveform. Table 14.17 lists the registers used in IEBus mode and the register values set. Figure 14.30 shows the functions of bus collision detect function related bits. If the TxD2 pin output level and RxD2 pin input level do not match, a UART2 bus collision detect interrupt request is generated. Table 14.
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14. Serial I/O M16C/29 Group (1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxD2 RxD2 Input to TA0IN Timer A0 If ABSCS is set to 1, bus collision is determined when timer .
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14. Serial I/O M16C/29 Group 14.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected. Table 14.18 lists the specifications of SIM mode. Table 14.19 lists the registers used in the SIM mode and the register values set. Table 14.
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14. Serial I/O M16C/29 Group Table 14.
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14.
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14. Serial I/O M16C/29 Group Figure 14.32 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. MCU SIM card TxD2 RxD2 Figure 14.32 SIM Interface Connection 14.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in theU2C1 register to 1. • When receiving The parity error signal is output when a parity error is detected while receiving data. This is achieved by pulling the TxD2 output low with the timing shown in Figure 14.
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14. Serial I/O M16C/29 Group 14.1.6.2 Format • Direct Format Set the PRY bit in the U2MR register to 1, the UFORM bit in U2C0 register to 0 and the U2LCH bit in U2C1 register to 0. • Inverse Format Set the PRY bit to 0, UFORM bit to 1 and U2LCH bit to 1. Figure 14.34 shows the SIM interface format.
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14. Serial I/O M16C/29 Group 14.2 SI/O3 and SI/O4 Note The SI/O4 interrupt of peripheral function interrupt is not available in the 64-pin package. SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os. Figure 14.35 shows the block diagram of SI/O3 and SI/O4, and Figure 14.36 shows the SI/O3 and SI/O4related registers. Table 14.20 shows the specifications of SI/O3 and SI/O4.
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14.
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14. Serial I/O M16C/29 Group Table 14.20 SI/O3 and SI/O4 Specifications Item Specification Transfer data format Transfer clock • Transfer data length: 8 bits • The SMi6 bit in the SiC (i=3, 4) register is set to 1 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO. n=Setting value of SiBRG register • SMi6 bit is set to 0 (external clock) : Input from CLKi pin (1) 0016 to FF16.
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14. Serial I/O M16C/29 Group 14.2.1 SI/Oi Operation Timing Figure 14.37 shows the SI/Oi operation timing 1.5 cycle (max) (3) SI/Oi internal clock "H" "L" CLKi output "H" "L" Signal written to the SiTRR register "H" "L" (2) SOUTi output "H" "L" SINi input "H" "L" SiIC register IR bit D0 D1 D2 D3 D4 D5 D6 D7 1 0 i= 3, 4 NOTES: 1.
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14. Serial I/O M16C/29 Group 14.2.3 Functions for Setting an SOUTi Initial Value If the SMi6 bit in SiC register is set to 0 (external clock), the SOUTi pin output level can be fixed high or low when not transferring data. However, when transmitting data consecutively, the last bit (bit 0) value of the last transmitted data is retained between the sccessive data transmissions. Figure 14.39 shows the timing chart for setting an SOUTi initial value and how to set it.
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15. A/D Converter M16C/29 Group 15. A/D Converter Note Ports P04 to P07(AN04 to AN07), P10 to P13(AN20 to AN23) and P95 to P97(AN25 to AN27) are not available in 64-pin package. Do not use port P04 to P07(AN04 to AN07), P10 to P13(AN20 to AN23) and P95 to P97(AN25 to AN27) as analog input pins in 64-pin package. The MCU contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier.
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15.
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15. A/D Converter M16C/29 Group A/D Conversion Status Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADSTAT0 Bit Symbol Address 03D316 After reset 0016 Bit Name Function ADERR0 AN1 trigger status flag ADERR1 Conversion termination flag 0: Conversion not terminated 1: Conversion terminated by Timer B0 underflow (b2) 0: AN1 trigger did not occur during AN0 conversion 1: AN1 trigger occured during AN0 conversion RW RW RW Nothing is assigned. If necessary, set to 0.
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15.
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15. A/D Converter M16C/29 Group 15.1 Operating Modes 15.1.1 One-Shot Mode In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table 15.3 shows the one-shot mode specifications. Figure 15.6 shows the operation example in one-shot mode. Figure 15.7 shows registers ADCON0 to ADCON2 in one-shot mode. Table 15.
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15. A/D Converter M16C/29 Group 15.1.2 Repeat mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 15.4 shows the repeat mode specifications. Figure 15.8 shows the operation example in repeat mode. Figure 15.9 shows the ADCON0 to ADCON2 registers in repeat mode. Table 15.4 Repeat Mode Specifications Item Specification Function Bits CH2 to CH0 in the ADCON0 register and the ADGSEL1 to ADGSEL0 bits in the ADCON2 register select pins.
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15. A/D Converter M16C/29 Group 15.1.3 Single Sweep Mode In single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital code. Table 15.5 shows the single sweep mode specifications. Figure 15.10 shows the operation example in single sweep mode. Figure 15.11 shows the ADCON0 to ADCON2 registers in single sweep mode. Table 15.
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15. A/D Converter M16C/29 Group 15.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a digital code. Table 15.6 shows the repeat sweep mode 0 specifications. Figure 15.12 shows the operation example in repeat sweep mode 0. Figure 15.13 shows the ADCON0 to ADCON2 registers in repeat sweep mode 0. Table 15.
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15.
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15. A/D Converter M16C/29 Group 15.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage is applied to the all selected pins are converted to a digital code, with mainly used in the selected pins. Table 15.7 shows the repeat sweep mode 1 specifications. Figure 15.14 shows the operation example in repeat sweep mode 1. Figure 15.15 shows registers ADCON0 to ADCON2 in repeat sweep mode 1. Table 15.
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15.
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M16C/29 Group 15. A/D Converter 15.1.6 Simultaneous Sample Sweep Mode In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-byone to a digital code. The input voltages of AN0 and AN1 are sampled simultaneously using two circuits of sample and hold circuit. Table 15.8 shows the simultaneous sample sweep mode specifications. Figure 15.16 shows the operation example in simultaneous sample sweep mode. Figure 15.17 shows registers ADCON0 to ADCON2 and Figure 15.
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15. A/D Converter M16C/29 Group A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON0 Address 03D6 16 Bit Symbol After Reset 00000XXX 2 Bit Name Function RW RW CH0 CH1 Analog input pin select bit Invalid in repeat sweep mode 0 RW RW CH2 MD0 b4 b3 RW MD1 A/D operation mode select bit 0 TRG Trigger select bit See Table 15.9 RW ADST A/D conversion start flag 0: A/D conversion disabled 1: A/D conversion started RW CKS0 Frequency select bit 0 See Table 15.
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M16C/29 Group 15. A/D Converter A/D Trigger Control Register (1) b7 b6 b5 b4 b3 b2 0 b1 Symbol ADTRGCON b0 1 1 Bit Symbol Address 03D216 After Reset 0016 Bit Name Function A/D operation mode select 1: Simultaneous sample sweep mode or delayed trigger mode 0, 1 bit 2 RW DTE A/D operation mode select 0: Other than delayed trigger mode 0, 1 bit 3 RW HPTRG0 AN0 trigger select bit See Table 15.
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15. A/D Converter M16C/29 Group 15.1.7 Delayed Trigger Mode 0 In delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The Timer B0 underflow starts a single sweep conversion. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted until the Timer B1 underflow is generated.
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M16C/29 Group 15.
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M16C/29 Group 15.
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M16C/29 Group 15. A/D Converter A/D Trigger Control Register (1) b7 b6 b5 b4 b3 b2 b1 Symbol ADTRGCON b0 1 1 1 1 Bit Symbol Address 03D216 After Reset 0016 Bit Name Function SSE A/D operation mode select Simultaneous sample sweep mode or bit 2 delayed trigger mode 0, 1 RW DTE A/D operation mode select bit 3 Delayed trigger mode 0, 1 RW HPTRG0 AN0 trigger select bit See Table 15.11 RW HPTRG1 AN1 trigger select bit See Table 15.11 RW (b7-b4) Nothing is assigned.
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15. A/D Converter M16C/29 Group 15.1.8 Delayed Trigger Mode 1 In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a ___________ digital code. When the input of the ADTRG pin (falling edge) changes state from “H” to “L”, a single sweep conversion is started. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted ___________ until the second ADTRG pin falling edge is generated.
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M16C/29 Group 15.
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15.
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M16C/29 Group 15.
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15. A/D Converter M16C/29 Group A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 0 0 0 1 1 1 Address 03D616 Bit Symbol CH0 After Reset 00000XXX 2 Bit Name Function b2 b1 b0 Analog input pin select bit 1 1 1: Set to 111b in delayed trigger mode 1 RW CH2 MD1 TRG RW RW CH1 MD0 RW A/D operation mode select bit 0 Trigger select bit b4 b3 0 0 : One-shot mode or delayed trigger mode 0,1 Refer to Table 15.
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M16C/29 Group 15. A/D Converter A/D Trigger Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 1 Symbol ADTRGCON Bit Symbol Address 03D216 After Reset 0016 Bit Name Function SSE A/D operation mode select Simultaneous sample sweep mode or delayed trigger mode 0, 1 bit 2 RW DTE A/D operation mode select bit 3 Delayed trigger mode 0, 1 RW HPTRG0 AN0 trigger select bit See Table 15.13 RW HPTRG1 AN1 trigger select bit See Table 15.13 RW (b7-b4) Nothing is assigned.
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15. A/D Converter M16C/29 Group 15.2 Resolution Select Function The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to 1 (10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the ADi register (i=0 to 7). When the BITS bit is set to 0 (8-bit precision), the A/D conversion result is stored into bits 7 to 0 in the ADi register. 15.
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M16C/29 Group 15. A/D Converter 15.5 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 15.29 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor equivalent circuit be R0, MCU’s internal resistance be R, precision (error) of the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8bit mode).
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16. Multi-master I2C bus Interface The multi-master I2C bus interface is a serial communication circuit based on Philips I2C bus data transfer format, equipped with arbitration lost detection and synchronous functions. Figure 16.1 shows a block diagram of the multi-master I2C bus interface and Table 16.1 lists the multi-master I2C bus interface functions.
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S3D0 b7 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 256 of 458 Figure 16.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 2 I C0 Address Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol S0D0 0 Bit Symbol (b0) Address 02E216 Bit Name Reserved bit page 257 of 458 Set to 0 RW RW RW SAD1 RW SAD3 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 Function SAD0 SAD2 Figure 16.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group I2C0 Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol S00 Address 02E016 After Reset XX16 Function RW Transmit/receive data are stored. In master transmit mode, the start condition/stop condition are triggered by writing data to the register (refer to 16.9 START Condition Generation Method and 16.11 STOP Condition Generation Method). Start transmitting/receiving data while synchronizing with SCL RW(1) NOTE: 1.
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16.
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16.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group I 2 C0 Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol S4D0 Bit Symbol TOE TOF TOSEL ICK2 Address 02E716 Bit Name RW Time out detection flag 0: Not detected 1: Detected RO Time out detection time select bit 0: Long time 1: Short time RW I2C bus system clock select bits b5 b4 b3 RW 0 0 0 VIIC set by ICK1 and ICK0 bits in S3D0 register 0 0 1 VIIC = 1/2.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group I 2 C0 Start/stop Condition Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol S2D0 Bit Symbol Address 02E516 Bit Name After Reset 00011010 2 Function RW SSC0 SSC1 SSC2 RW START/STOP condition setting bits(1) Setting for detection condition of START/STOP condition. See Table 16.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.1 I2C0 Data Shift Register (S00 register) The S00 register is an 8-bit data shift register to store a received data and to write a transmit data. When a transmit data is written to the S00 register, the transmit data is synchronized with a SCL clock and the data is transferred from bit 7. Then, every one bit of the data is transmitted, the register's content is shifted for one bit to the left.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.3 I2C0 Clock Control Register (S20 register) The S20 register is used to set theACK control, SCL mode and the SCL frequency. 16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4) These bits control the SCL frequency. See Table 16.3 . 16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE) The FAST MODE bit selects SCL mode. When the FAST MODE bit is set to 0, standard clock mode is entered. When it is set to 1, high-speed clock mode is entered.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group → → → → → Table 16.3 Setting values of S20 register and SCL frequency Setting value of CCR4 to CCR0 SCL frequency (at VIIC=4MHz, unit : kHz) (1) CCR4 CCR3 CCR2 CCR1 CCR0 Standard clock mode High-speed clock mode 0 0 0 0 0 Setting disabled Setting disabled 0 0 0 0 1 Setting disabled Setting disabled 0 0 0 1 0 Setting disabled Setting disabled 0 0 0 1 1 - (2) 333 0 0 1 0 0 - (2) 250 0 0 1 0 1 100 400 (3) 0 0 1 1 0 83.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.4 I2C0 Control Register 0 (S1D0) The S1D0 register controls data communication format. 16.4.1 Bits 0 to 2: Bit Counter (BC0–BC2) Bits BC2 to BC0 decide how many bits are in one byte data transferred next. After the selected numbers of bits are transferred successfully, I2C bus interface interrupt request is gnerated and bits BC2 to BC0 are reset to 0002.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.4.5 Bit 7: I2C bus Interface Pin Input Level Select Bit (TISS) The TISS bit selects the input level of the SCL and SDA pins for the multi-master I2C bus interface. When the TISS bit is set to 1, the P20 and P21 become the SMBus input level. Write 1 to IHR bit IHR bit A reset signal to I2C bus interface circuit 2.5 VIIC cycles Figure 16.10 The timing of reset to the I2C bus interface circuit Rev. 1.12 Mar.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.5 I2C0 Status Register (S10 register) The S10 register monitors the I2C bus interface status. When using the S10 register to check the status, use the 6 low-order bits for read only. 16.5.1 Bit 0: Last Receive Bit (LRB) The LRB bit stores the last bit value of received data. It can also be used to confirm whether ACK is received.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.5.5 Bit 4: I2C bus Interface Interrupt Request Bit (PIN) The PIN bit generates an I2C bus interface interrupt request signal. Every one byte data is ransferred, the PIN bit is changed from 1 to 0. At the same time, an I2C bus interface interrupt request is generated.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX) This TRX bit decides a transfer direction for data communication. When the TRX bit is set to 0, receive mode is entered and data is received from a transmit device. When the TRX bit is set to 1, transmit mode is entered, and address data and control data are output to the SDAMM, synchronized with a clock generated in the SCLMM.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.6 I2C0 Control Register 1 (S3D0 register) The S3D0 register controls the I2C bus interface circuit. 16.6.1 Bit 0 : Interrupt Enable Bit by STOP Condition (SIM ) The SIM bit enables the I2C bus interface interrupt request by detecting a STOP condition. If the SIM bit is set to 1, the I2C bus interface interrupt request is generated by the STOP condition detect (no need to change in the PIN flag). 16.6.
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16.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM Bits SDAM/SCLM can monitor the logic value of the SDA and SCL output signals from the I 2C bus interface circuit. The SDAM bit monitors the SDA output logic value. The SCLM bit monitors the SCL output logic value. The SDAM and SCLM bits are read-only. If necessary, set them to 0. 16.6.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.7 I2C0 Control Register 2 (S4D0 Register) The S4D0 register controls the error communication detection. If the SCL clock is stopped counting dring data transfer, each device is stopped, staying online. To avoid the situation, the I2C bus interface circuit has a function to detect the time-out when the SCL clock is stopped in high-level ("H") state for a specific period, and to generate an I2C bus interface interrupt request. See Figure 16.13.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) The TOE bit enables the time-out detection function. When the TOE bit is set to 1, time-out is detected and the I2C bus interface interrupt request is generated when the following conditions are met. 1) the BB flag in the S10 register is set to 1 (bus busy) 2) the SCL clock stops for time-out detection period while high-level ("H") signal is maintained (see Table 16.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.8 I2C0 START/STOP Condition Control Register (S2D0 Register) The S2D0 register controls the START/STOP condition detections. 16.8.1 Bit0-Bit4: START/STOP Condition Setting Bits (SSC0-SSC4) The SCL release time and the set-up and hold times are mesured on the base of the I2C bus system clock (VIIC). Therefore, the detection conditions changes, depending on the oscillation frequency (XIN) and the I2C bus system clock select bits.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.9 START Condition Generation Method Set the MST bit, TRX bit and BB flags in the S10 register to 1 and set the PIN bit and 4 low-order bits in the S10 register to 0 simultaneously, to enter START condition standby mode, when the ES0 bit in the S1D0 register is set to 1 (I2C bus interface enabled) and the BB flag is set to 0 (bus free).
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.10 START Condition Duplicate Protect Function A START condition is generated when verifying that the BB flag in the S10 register does not use buses. However, if the BB flag is set to 1 (bus busy) by the START condition which other master device generates immediately after the BB flag is verified, the START condition is suspended by the START condition duplicate protect function.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group S00 register SCL Setup time Hold time SDA Figure 16.16 Start condition generation timing diagram S00 register SCL Hold time Setup time SDA Figure 16.17 Stop condition generation timing diagram Table 16.8 Start/Stop generation timing table Start/Stop Condition Generation Select Bit Standard Clock Mode High-speed Clock Mode 0 5.0 µs (20 cycles) 2.5 µs (10 cycles) 1 13.0 µs (52 cycles) 6.5 µs (26 cycles) 0 5.0 µs (20 cycles) 2.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.12 START/STOP Condition Detect Operation Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. Bits SSC4 to SSC0 in the S2D0 register set the START/STOP conditions. The START/STOP condition can be detected only when the input signal of the SCLMM and SDAMM met the following conditions: the SCL release time, the set-up time, and the hold time (see Table 16.10).
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.13 Address Data Communication This section describes data transmit control when a master transferes data or a slave receives data in 7-bit address format. Figure 16.20 (1) shows a master transmit format.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.13.2 Example of Slave Receive For example, a slave receives data as shown below when following conditions are met: high-speed clock mode, SCL frequency of 400 kHz, ACK clock added and addressing format.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group 16.14 Precautions (1) Access to the registers of I2C bus interface circuit The following is precautions when read or write the control registers of I2C bus interface circuit •S00 register Do not rewrite the S00 register during data transfer. If the bits in the S00 register are rewritten, the bit counter for transfer is reset and data may not be transferred successfully.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group SCL SDA BB flag Bit reset signal Related bits 1.5 VIIC cycle MST TRX Figure 16.21 The bit reset timing (The STOP condition detection) SCL SDA BB flag Bit reset signal Related bits BC2 - BC0 TRX (in slave mode) Figure 16.22 The bit reset timing (The START condition detection) SCL PIN bit AA AAA Bit reset signal 2VIIC cycle Bit set signal 1VIIC cycle AAAAA AAAAA AAAAA The bits referring to reset The bits referring to set Figure 16.
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16. MULTI-MASTER I2C bus INTERFACE M16C/29 Group (2) Generation of RESTART condition In order to generate a RESTART condition after 1-byte data transfer, write E016 to the S10 register, enter START condition standby mode and leave the SDAMM open. Generate a START condition trigger by setting the S00 register after inserting a sufficient software wait until the SDAMM outputs a high-level ("H") signal. Figure 16.24 shows the RESTART condition generation timing.
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17. CAN Module M16C/29 Group 17. CAN Module The CAN (Controller Area Network) module for the M16C/29 Group of MCUs is a communication controller implementing the CAN 2.0B protocol. The M16C/29 Group contains one CAN module which can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats. Figure 17.1 shows a block diagram of the CAN module. External CAN bus driver and receiver are required.
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17. CAN Module M16C/29 Group 17.1 CAN Module-Related Registers The CAN0 module has the following registers. (1) CAN Message Box A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN. • Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission and reception. • A program can define whether a slot is defined as transmitter or receiver.
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17. CAN Module M16C/29 Group 17.1.1 CAN0 Message Box Table 17.1 shows the memory mapping of the CAN0 message box. It is possible to access to the message box in byte or word. Mapping of the message contents differs from byte access to word access. Byte access or word access can be selected by the MsgOrder bit of the C0CTLR register. Table 17.
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17. CAN Module M16C/29 Group Figures 17.2 and 17.3 show the bit mapping in each slot in byte access and word access. The content of each slot remains unchanged unless transmission or reception of a new message is performed.
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17. CAN Module M16C/29 Group 17.1.2 Acceptance Mask Registers Figures 17.4 and 17.5 show the C0GMR register, the C0LMAR register, and the C0LMBR register, in which bit mapping in byte access and word access are shown.
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17. CAN Module M16C/29 Group 17.1.3 CAN SFR Registers 17.1.3.1 C0MCTLj Register (j = 0 to 15) Figure 17.6 shows the C0MCTLj register.
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17. CAN Module M16C/29 Group 17.1.3.2 C0CTLR Register Figure 17.7 shows the C0CTLR register.
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17. CAN Module M16C/29 Group 17.1.3.3 C0STR Register Figure 17.8 shows the C0STR register. CAN0 Status Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0STR Bit Symbol Address 021216 After Reset 0016 Bit Name Function RW b3 b2 b1 b0 MBOX TrmSucc Active slot bits(1) Successful transmission flag(1) 0 0 0 0: Slot 0 0 0 0 1: Slot 1 0 0. 1 0: Slot 2 ..
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17. CAN Module M16C/29 Group 17.1.3.4 C0SSTR Register Figure 17.9 shows the C0SSTR register. CAN0 Slot Status Register (b15) b7 (b8) b0 b7 b0 Symbol C0SSTR Address 021516, 021416 Function Slot status bits Each bit corresponds to the slot with the same number After Reset 000016 Setting Values 0: Reception slot The message has been read. Transmission slot Transmission is not completed. 1: Reception slot The message has not been read. Transmission slot Transmission is completed Figure 17.
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17. CAN Module M16C/29 Group 17.1.3.5 C0ICR Register Figure 17.10 shows the C0ICR register. CAN0 Interrupt Control Register (1) (b15) b7 (b8) b0 b7 b0 Symbol C0ICR Address 021716, 021616 After Reset 000016 Function Setting Values 0: Interrupt disabled Interrupt enable bits: 1: Interrupt enabled Each bit corresponds with a slot with the same number. Enabled/disabled of successful transmission interrupt or successful reception interrupt can be selected RW RW NOTE: 1.
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17. CAN Module M16C/29 Group 17.1.3.7 C0CONR Register Figure 17.12 shows the C0CONR register. CAN0 Configuration Register(2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0CONR Bit symbol Address 021A16 After reset Undefined Bit name Function RW b3 b2 b1 b0 0 0 0 0: Divide-by-1 of fCAN 0 0 0 1: Divide-by-2 of fCAN 0 0 1 0: Divide-by-3 of fCAN .....
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17. CAN Module M16C/29 Group 17.1.3.8 C0RECR Register Figure 17.13 shows the C0RECR register. CAN0 Receive Error Count Register b7 b0 Symbol C0RECR Address 021C16 After Reset 0016 Function Counter Value Reception error counting function The value is incremented or decremented according to the CAN module's error status 0016 to FF16 (1) RW RO NOTE: 1. The value is undefined in bus off state. Figure 17.13 C0RECR Register 17.1.3.9 C0TECR Register Figure 17.14 shows the C0TECR register.
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17. CAN Module M16C/29 Group 17.1.3.10 C0TSR Register Figure 17.15 shows the C0TSR register. CAN0 Time Stamp Register(1) (b15) b7 (b8) b0 b7 b0 Symbol C0TSR Address 021F16, 021E16 After Reset 000016 Function Counter Value Time stamp function 000016 to FFFF16 RW RO NOTE: 1. Use a 16-bit data for reading. Figure 17.15 C0TSR Register 17.1.3.11 C0AFS Register Figure 17.16 shows the C0AFS register.
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17. CAN Module M16C/29 Group 17.2 Operating Modes The CAN module has the following four operating modes. • CAN Reset/Initialization Mode • CAN Operating Mode • CAN Sleep Mode • CAN Interface Sleep Mode Figure 17.17 shows transition between operating modes.
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17. CAN Module M16C/29 Group 17.2.2 CAN Operating Mode The CAN operating mode is activated by setting the Reset bit in the C0CTLR register to 0. If the Reset bit is set to 0, check that the State_Reset bit in the C0STR register is set to 0.
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17. CAN Module M16C/29 Group 17.2.4 CAN Interface Sleep Mode The CAN interface sleep mode is activated by setting the CCLK3 bit in the CCLKR register to 1. It should never be activated but only via the CAN sleep mode. Entering the CAN interface sleep mode instantly stops the clock supply to the CPU Interface in the module and thereby reduces power dissipation. 17.2.5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specification.
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17. CAN Module M16C/29 Group 17.3 Configuration of the CAN Module System Clock The M16C/29 Group has a CAN module system clock select circuit. Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit in the C0CONR register. For the CCLKR register, refer to 7. Clock Generation Circuit. Figure 17.19 shows a block diagram of the clock generation circuit of the CAN module system.
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17. CAN Module M16C/29 Group 17.3.2 Bit-rate Bit-rate depends on f1, the division value of the CAN module system clock, the division value of the baud rate prescaler, and the number of Tq of one bit. Table 17.2 shows the examples of bit-rate. Table 17.2 Examples of Bit-rate Bit-rate 20MHz 1Mbps 10Tq (1) 500kbps 10Tq (2) 20Tq (1) 125kbps 10Tq (8) 20Tq (4) 83.3kbps 10Tq (12) 20Tq (6) 33.
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17. CAN Module M16C/29 Group 17.4 Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message. The C0GMR register, the C0LMAR register, and the C0LMBR register can perform masking to the standard ID and the extended ID of 29 bits. The C0GMR register corresponds to slots 0 to 13, the C0LMAR register corresponds to slot 14, and the C0LMBR register corresponds to slot 15.
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17. CAN Module M16C/29 Group 17.5 Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search. The IDs to receive are registered in the data table; a received ID is stored in the C0AFS register, and table search is performed with a decoded received ID. The acceptance filter support unit can be used for the IDs of the standard frame only. The acceptance filter support unit is valid in the following cases.
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17. CAN Module M16C/29 Group 17.6 BasicCAN Mode When the BasicCAN bit in the C0CTLR register is set to 1 (Basic CAN mode enabled), slots 14 and 15 correspond to Basic CAN mode. During normal operations, individual slots can select either data frame or remote frame by CPU setting. However, in Basic CAN mode, both frames can be selected. When slots 14 and 15 are defined as reception slots in Basic CAN mode, received messages are stored in slots 14 and 15 alternately.
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17. CAN Module M16C/29 Group 17.7 Return from Bus off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by setting the RetBusOff bit in the C0CTLR register to 1 (Force return from bus off). At this time, the error state changes from bus off state to error active state.
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17. CAN Module M16C/29 Group 17.10 Reception and Transmission Configuration of CAN Reception and Transmission Mode Table 17.3 shows configuration of CAN reception and transmission mode. Table 17.3 Configuration of CAN Reception and Transmission Mode TrmReq RecReq Remote RspLock 0 0 - - 0 1 1 0 0 1 0 0 Communication mode of the slot Communication environment configuration mode: configure the communication mode of the slot. Configured as a reception slot for a data frame.
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17. CAN Module M16C/29 Group 17.10.1 Reception Figure 17.25 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown C0MCTLj register (j = 0 to 15) and leads to losing/overwriting of the first message. SOF ACK EOF IFS SOF ACK EOF IFS CANbus InvalData bit (2) NewData bit (2) (5) (4) (5) MsgLost bit CAN0 Successful Reception Interrupt (5) (3) (1) RecSucc bit MBOX bit Receive slot No.
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17. CAN Module M16C/29 Group 17.10.2 Transmission Figure 17.26 shows the timing of the transmit sequence. SOF ACK EOF IFS SOF (1) (4) TrmActive bit (1) (2) (3) SentData bit (3) CAN0 Successful Transmission Interrupt (3) TrmState bit (1) (2) TrmSucc bit MBOX bit Transmission slot No. C0STR register TrmReq bit C0MCTLj register CTx j = 0 to 15 Figure 17.
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17. CAN Module M16C/29 Group 17.11 CAN Interrupts The CAN module provides the following CAN interrupts.
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18. CRC Calculation Circuit M16C/29 Group 18. CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation detects errors in blocks of data. The MCU uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) or CRC-16 (X16 + X15 + X2 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of bytes. The code is updated in the CRC data register everytime one byte of data is transferred to a CRC input register.
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18.
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18. CRC Calculation Circuit M16C/29 Group b15 b0 (1) Setting 000016 (initial value) CRD data register CRCD [03BD16, 03BC16] b7 b0 (2) Setting 0116 CRC input register CRCIN [03BE16] 2 cycles After CRC calculation is complete b0 b15 CRD data register CRCD [03BD16, 03BC16] 118916 Stores CRC code The code resulting from sending 0116 in LSB first mode is (10000 0000).
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M16C/29 Group 19. Programmable I/O Ports 19. Programmable I/O Ports Note Ports P04 to P07, P10 to P14 , P34 to P37 and P95 to P97 are not available in 64-pin package. The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 71 lines P0, P1, P2, P3, P6, P7, P8, P9, P10 (except P94) for the 80-pin package, or 55 lines P00 to P03, P15 to P17, P2, P30 to P33, P6, P7, P8, P90 to P93, P10 for the 64-pin package.
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19. Programmable I/O Ports M16C/29 Group 19.5 Pin Assignment Control Register (PACR) Figure 19.10 shows the PACR register. After reset, set bits PACR2 to PACR0 in the PACR register before a signal is input or output to each pin. When bits PACR2 to PACR0 are not set, some pins do not function as I/O ports. Bits PACR2 to PACR0: control pins to be used Value after reset: 0002. To select the 80-pin package, set the bits to 0112. To select the 64-pin package, set the bits to 0102.
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M16C/29 Group 19.
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19. Programmable I/O Ports M16C/29 Group Pull-up selection Direction register P20, P21, P70 to P73 Port latch Data bus "1" Output Switching between CMOS and Nch (1) Input to respective peripheral functions Pull-up selection P82 to P84 Direction register Data bus Port latch (1) Input to respective peripheral functions Pull-up selection Direction register P31, P62, P66, P77 Data bus Port latch (1) Input to respective peripheral functions NOTE: 1. symbolizes a parasitic diode.
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M16C/29 Group 19. Programmable I/O Ports Pull-up selection Direction register P63, P67 “1” Output Port latch Data bus (1) Switching between CMOS and Nch Pull-up selection P85 NMI Enable Direction register Port latch Data bus (1) Digital Debounce NMI Interrupt Input NMI Enable SD Pull-up selection P91, P92, P97, P104 to P107 Direction register Data bus Port latch (1) Analog input Input to respective peripheral functions NOTE: 1. symbolizes a parasitic diode.
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19. Programmable I/O Ports M16C/29 Group P90, P95 (inside dotted-line included) P93, P96 (inside dotted-line not included) Data bus Pull-up selection Direction register 1 Port latch Output (1) Analog input Input to respective peripheral functions Pull-up selection Direction register P87 Data bus Port latch (1) fc Rf Pull-up selection Rd Direction register P86 Data bus Port latch (1) NOTE: 1. symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc.
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M16C/29 Group 19. Programmable I/O Ports CNVSS CNVSS signal input (1) RESET RESET signal input (1) NOTE: 1. symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 19.5 I/O Pins Rev. 1.12 Mar.
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19.
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M16C/29 Group 19.
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19. Programmable I/O Ports M16C/29 Group Pull-up Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit Symbol Address 03FC16 After Reset 0016 Bit Name PU00 P00 to P03 pull-up PU01 P04 to P07 pull-up PU02 P10 to P13 pull-up PU03 P14 to P17 pull-up PU04 P20 to P23 pull-up PU05 P24 to P27 pull-up PU06 P30 to P33 pull-up PU07 P34 to P37 pull-up Function 0: Not pulled up 1: Pulled up (1) RW RW RW RW RW RW RW RW RW NOTE: 1.
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M16C/29 Group 19. Programmable I/O Ports Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PCR Address 03FF16 Bit symbol PCR0 (b7-b1) After Reset 0016 Bit Name Port P1 control bit Function RW Operation performed when the P1 register is read 0: When the port is set for input, the input levels of P10 to P17 RW pins are read. When set for output, the port latch is read. 1: The port latch is read regardless of whether the port is set for input or output. Nothing is assigned.
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19. Programmable I/O Ports M16C/29 Group NMI Digital Debounce Register (1,2) b7 b0 Symbol NDDR Address 033E16 After Reset FF16 Function If the set value =n, - n = 0 to FE16; a signal with pulse width, greater than (n+1)/f8, is input into NMI / SD - n = FF16; the digital debounce filter is disabled and all signals are input Setting Range RW 0016 to FF16 RW NOTES: 1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to 1 (write enable). 2.
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M16C/29 Group • Example 19. Programmable I/O Ports of INT5 Digital Debounce Function (if P17DDR = 0316) Digital Debounce Filter f8 P17 Data Bus Clock Port In Signal Out Reload Value (write) To INT5 Count Value (read) Data Bus f8 Reload Value FF 03 Port In Signal Out Count Value 03 FF 1 02 01 03 3 2 4 03 Reload Value (continued) 02 01 FF 00 5 FF Port In (continued) Signal Out (continued) Count Value (continued) 03 FF 02 01 6 00 03 FF 7 8 FF 02 9 1.
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19. Programmable I/O Ports M16C/29 Group Table 19.1 Unassigned Pin Handling in Single-chip Mode Pin Name Setting Ports P0 to P3, P6 to P10 Enter input mode and connect each pin to VSS via a resistor (pull-down); or enter output mode and leave the pins open (1,2,4) XOUT Leave pin open (3) XIN Connect pin to VCC via a resistor (pull-up) (5) AVCC Connect pin to VCC AVSS, VREF Connect pin to VSS NOTES: 1.
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20. Flash Memory Version M16C/29 Group 20. Flash Memory Version 20.1 Flash Memory Performance In the flash memory version, rewrite operation to the flash memory can be performed in four modes: CPU rewrite mode, standard serial I/O mode, parallel I/O mode, and CAN I/O mode. Table 20.1 lists specifications of the flash memory version. (Refer to Table 1.1 or Table 1.2 for the items not listed in Table 20.1. Table 20.
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20. Flash Memory Version M16C/29 Group Table 20.2. Flash Memory Rewrite Modes Overview Flash memory rewrite mode Function Areas which can be rewritten Operation mode ROM programmer CPU rewrite mode Standard serial I/O mode The user ROM area is The user ROM area rewritten when the CPU is rewritten using a excutes software dedicated serial command programmer. from the CPU.
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20. Flash Memory Version M16C/29 Group 20.2 Memory Map The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 20.1 to 20.3 show a block diagram of the flash memory. The user ROM area has space to store the MCU operation program in single-chip mode and two 2-Kbyte spaces: the block A and B. The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite, standard serial I/O, parallel I/O, or CAN I/O mode.
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20. Flash Memory Version M16C/29 Group 00F00016 00F7FF16 00F80016 00FFFF16 (Data space) Block B :2K bytes (2) Block A :2K bytes (2) (Program space) 0E800016 Block 4 : 32K bytes (5) 0EFFFF16 0F000016 Block 3 : 32K bytes (5) 0F7FFF16 0F800016 Block 2 : 16K bytes Block 2 : 16K bytes (5) 0FBFFF16 0FC00016 NOTES: 1. To specify a block, use the maximum even address in the block. 2. Blocks A and B are enabled for use when the PM10 bit in the PM1 register is set to 1. 3.
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20. Flash Memory Version M16C/29 Group 00F00016 00F7FF16 00F80016 00FFFF16 (Data space) Block B :2K bytes(2) Block A :2K bytes(2) (Program space) 0E000016 Block 5 : 32K bytes(5) 0E7FFF16 0E800016 Block 4 : 32K bytes (5) 0EFFFF16 0F000016 Block 3 : 32K bytes (5) 0F7FFF16 0F800016 Block 2 : 16K bytes Block 2 : 16K bytes (5) 0FBFFF16 0FC00016 Block 1 : 8K bytes(3) 0FDFFF16 0FE00016 Block 0 : 8K bytes (3) 0FFFFF16 NOTES: 1. To specify a block, use the maximum even address in the block. 2.
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20. Flash Memory Version M16C/29 Group 20.3 Functions To Prevent Flash Memory from Rewriting The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code check function for standard input/output mode to prevent the flash memory from reading or rewriting. 20.3.1 ROM Code Protect Function The ROM code protect function disables reading or changing the contents of the on-chip flash memory in parallel I/O mode. Figure 20.4 shows the ROMCP address.
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20. Flash Memory Version M16C/29 Group ROM Code Protect Control Address(5) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 Symbol ROMCP Address 0FFFFF16 Bit Name Bit Symbol (b5-b0) ROMCP1 Factory Setting FF16 (4) Function Reserved Bit Set to 1 ROM Code Protect Level 1 Set Bit (1, 2, 3, 4) b7 b6 00: 01: Enables protect 10: 11: Disables protect } RW RW RW RW NOTES: 1.
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20. Flash Memory Version M16C/29 Group 20.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with MCU mounted on a board without using the ROM writer. The program and block erase commands are executed only in the user ROM area.
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20. Flash Memory Version M16C/29 Group 20.4.1 EW Mode 0 The MCU enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode enabled) and is ready to accept software commands. EW mode 0 is selected by setting the FMR11 bit in the FMR1 register to 0. To set the FMR01 bit to 1, set to 1 after first writing 0. The software commands control programming and erasing. The FMR0 register or the status register indicates whether a programming or erasing operations is completed.
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20. Flash Memory Version M16C/29 Group 20.5 Register Description Figure 20.6 shows the flash memory control register 0 and flash memory control register 1. Figure 20.7 shows the flash memory control register 4. 20.5.1 Flash Memory Control Register 0 (FMR0) •FMR 00 Bit The FMR00 bit indicates the operating state of the flash memory. Its value is 0 while the program, erase, or erase-suspend command is being executed, otherwise, it is 1.
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20. Flash Memory Version M16C/29 Group 20.5.2 Flash Memory Control Register 1 (FMR1) •FMR11 Bit EW mode 1 is entered by setting the FMR11 bit to 1 (EW mode 1). The FMR11 bit is valid only when the FMR01 bit is set to 1. •FMR16 Bit The combined setting of bits FMR02 and FMR16 enables program and erase in the user ROM area. To set the FMR16 bit to 1, first set it to 0 and then 1. The FMR16 bit is valid only when the FMR01 bit is set to 1 (CPU rewrite mode enable).
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20. Flash Memory Version M16C/29 Group Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol Address FMR0 After Reset 01B7 16 00000001 2 Bit Name Bit Symbol Function FMR00 RY/BY status flag 0: Busy (during writing or erasing) 1: Ready FMR01 CPU rewrite mode select bit (1) 0: Disables CPU rewrite mode (Disables software command) 1: Enables CPU rewrite mode (Enables software commands) FMR02 Block 0, 1 rewrite enable bit Set write protection for user ROM area (see Table 20.
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20. Flash Memory Version M16C/29 Group Low power consumption mode program Transfer a low power internal consumption mode program to RAM area Jump to the low power consumption mode program transferred to internal RAM area. (In the following steps, use the low-power consumption mode program or internal RAM area) Set the FMR01 bit to 1 after setting 0 (CPU rewrite mode enabled) (2) Set the FMSTP bit to 1 (flash memory stopped. Low power consumption state)(1) Switch the clock source of CPU clock.
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20. Flash Memory Version M16C/29 Group 20.6 Precautions in CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. 20.6.1 Operation Speed When the CPU clock source is the main clock, set the CPU clock frequency at 10 MHz or less with the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register, before entering CPU rewrite mode (EW mode 0 or EW mode 1).
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20. Flash Memory Version M16C/29 Group 20.6.6 DMA Transfer In EW mode 1, do not generate a DMA transfer while the FMR00 bit in the FMR0 register is set to 0. (during the auto-programming or auto-erasing). 20.6.7 Writing Command and Data Write the command codes and data to even addresses in the user ROM area. 20.6.8 Wait Mode When entering wait mode, set the FMR01 bit to 0 (CPU rewrite mode disabled) before executing the WAIT instruction. 20.6.
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20. Flash Memory Version M16C/29 Group 20.7 Software Commands Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing a command code, 8 high-order bits (D15–D8) are ignored. Table 20.
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20. Flash Memory Version M16C/29 Group 20.7.4 Program Command (4016) The program command writes 2-byte data to the flash memory. Auto program operation (data program and verify) start by writing xx4016 in the first bus cycle and data to the write address specified in the second bus cycle. The address value specified in the first bus cycle must be the same even address as the write address secified in the second bus cycle.
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20. Flash Memory Version M16C/29 Group 20.7.5 Block Erase Auto erase operation (erase and verify) start in the specified block by writing xx2016 in the first bus cycle and xxD016 to the highest-order even addresse of a block in the second bus cycle. The FMR00 bit in the FMR0 register indicates whether the auto-erase operation has been completed. The FMR00 bit is set to 0 (busy) during the auto-erase and 1 (ready) when the auto-erase operation is completed.
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20.
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20. Flash Memory Version M16C/29 Group 20.8 Status Register The status register indicates the operating status of the flash memory and whether or not erase or program operation is successfully completed. Bits FMR00, FMR06, and FMR07 in the FMR0 register indicate the status of the status register. Table 20.6 lists the status register.
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20. Flash Memory Version M16C/29 Group 20.8.4 Full Status Check If an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating a specific error. Therefore, execution results can be comfirmed by verifying these status bits (full status check). Table 20.7 lists errors and FMR0 register state. Figure 20.14 shows a flow chart of the full status check and handling procedure for each error. Table 20.
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20. Flash Memory Version M16C/29 Group Full status check FMR06 =1 and FMR07=1? YES Command sequence error NO NO FMR07= 0? Erase error YES NO FMR06= 0? Program error YES (1) Execute the clear status register command and set the status flag to 0 whether the command is entered. (2) Execute the command again after checking that the correct command is entered or the program command or the block erase command is not executed on the protected blocks.
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20. Flash Memory Version M16C/29 Group 20.9 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/29 group can be used to rewrite the flash memory user ROM area, while the MCU is mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer. Refer to the user’s manual included with your serial programmer for instruction. Table 20.8 lists pin description (flash memory standard serial input/output mode).
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20. Flash Memory Version M16C/29 Group Table 20.8 Pin Descriptions (Flash Memory Standard Serial I/O Mode) Pin Name VCC,VSS Power input CNVSS CNVS S I/O Descriptio n Apply the voltage guaranteed for Program and Erase to Vcc pin and 0 V to Vss pin. I Connect to Vcc pin. RESET Reset input I Reset input pin. While RESET pin is “L”, wait for td(ROC). XIN Clock input I XOUT Clock output O Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins.
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20.
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20. Flash Memory Version M16C/29 Group 20.9.2 Example of Circuit Application in Standard Serial I/O Mode Figure 20.17 shows an example of a circuit application in standard serial I/O mode 1 and Figure 20.18 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer.
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20. Flash Memory Version M16C/29 Group MCU SCLK TxD output TxD Monitor output BUSY RxD input RxD P86(CE) P16 (1) (1) CNVss P85(RP) (1) In this example, a selector controls the input voltage applied to CNVss to switch between single-chip mode and standard serial I/O mode. NOTE: 1. Set the following, either or both. - Connect the CE pin to Vcc - Connect the RP pin to Vss and the P16 pin to Vcc Figure 20.18 Circuit Application in Standard Serial I/O Mode 2 Rev. 1.12 Mar.
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20. Flash Memory Version M16C/29 Group 20.10 Parallel I/O Mode In parallel input/output mode, the user ROM can be rewritten by a parallel programmer supporting the M16C/29 group. Contact your parallel programmer manufacturer for more information on the parallel programmer. Refer to the user’s manual included with your parallel programmer for instructions. 20.10.1 ROM Code Protect Function The ROM code protect function prevents the flash memory from being read or rewritten. (Refer to 20.
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20. Flash Memory Version M16C/29 Group 20.11 CAN I/O Mode Note The CAN I/O mode is not available in M16C/29 T-ver./V-ver. In CAN I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a CAN programmer which is applicable for the M16C/29 group. For more information about CAN programmers, contact the manufacturer of your CAN programmer. For details on how to use, refer to the user’s manual included with your CAN programmer. Table 20.9 lists pin functions for CAN I/O mode.
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20. Flash Memory Version M16C/29 Group Table 20.9 Pin Functions for CAN I/O Mode Pin Name Description I/O Apply the voltage guaranteed for Program and Erase to Vcc pin and 0 V to Vss pin. VCC,VSS Power input CNVSS CNVSS I Connect to Vcc pin. RESET Reset input I Reset input pin. While RESET pin is "L" level, wait for td(ROC). XIN Clock input I XOUT Clock output O Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins.
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20. Flash Memory Version 33 34 35 36 37 38 39 40 41 42 43 44 49 32 50 31 51 30 52 29 53 28 54 27 M16C/29 Group (64-pin package) 55 57 25 23 16 15 14 13 12 11 10 9 8 7 17 6 18 64 5 19 63 4 20 62 3 21 61 2 22 60 1 59 Note RP Vcc RESET CE Vss Note Connect oscillator circuit NOTE: 1. Set following either or both in serial I/O mode while the RESET pin is held “L”.
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20.
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20. Flash Memory Version M16C/29 Group 20.11.2 Example of Circuit Application in CAN I/O Mode Figure 20.21 shows example of circuit application in CAN I/O mode. Refer to the user’s manual for CAN programmer to handle pins controlled by a CAN programmer. MCU TXD SCLK CAN transceiver (Note 1) P86(CE) (Note 1) CAN_H P92/CRx CAN_L P93/CTx P16 CNVss Reset input RESET User reset singnal P85(RP) (1) Control pins and external circuits vary with the CAN programmer.
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21. Electrical Characteristics (Normal-version) M16C/29 Group 21. Electrical Characteristics 21.1 Normal version Table 21.1 Absolute Maximum Ratings Condition Value Unit VCC Symbol Supply Voltage VCC=AVCC -0.3 to 6.5 V AVCC Analog Supply Voltage VCC=AVCC -0.3 to 6.5 V VI Input Voltage -0.3 to VCC+0.3 V -0.3 to VCC+0.
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M16C/29 Group 21. Electrical Characteristics (Normal-version) Table 21.2 Recommended Operating Conditions (Note 1) Symbol Standard Parameter Min. 2.7 Typ. Max. 5.5 Unit VCC AVCC Supply Voltage Analog Supply Voltage VSS Supply Voltage 0 V AVSS Analog Supply Voltage 0 V VIH Input High ("H") Voltage VIL Input Low ("L") Voltage VCC P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67, 0.7VCC P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107 0.
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21. Electrical Characteristics (Normal-version) M16C/29 Group Table 21.3 A/D Conversion Characteristics (Note 1) Symbol - Parameter Resolution Integral Nonlinearity Error INL Measurement Condition 10 bit 8 bit - Absolute Accuracy 10 bit 8 bit Standard Min. Typ. Max. Unit VREF=VCC 10 Bits VREF=VCC=5V ±3 LSB VREF=VCC=3.3V ±5 LSB VREF=VCC=3.3V ±2 LSB VREF=VCC=5V ±3 LSB VREF=VCC=3.3V ±5 LSB VREF=VCC=3.
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M16C/29 Group 21. Electrical Characteristics (Normal-version) Table 21.4 Flash Memory Version Electrical Characteristics (1) for 100/1000 E/W cycle products [Program Space and Data Space in U3 and U5: Program Space in U7 and U9] Symbol Standard Parameter Min. Typ.(2) ( 4 , 1 100/1000 1) Max. Unit - Program and Erase Endurance(3) - Word Program Time (VCC=5.0V, Topr=25° C) 75 600 µs - Block Erase Time (VCC=5.0V, Topr=25° C) 0.2 0.4 0.7 1.
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21. Electrical Characteristics (Normal-version) M16C/29 Group Table 21.6 Low Voltage Detection Circuit Electrical Characteristics (Note 1, Note 3) Symbol Parameter Measurement Condition Standard Min. Typ. Max. Unit Vdet4 Low Voltage Detection Voltage(1) 3.2 3.8 4.45 V Vdet3 Reset Space Detection Voltage(1) 2.3 2.8 3.4 V 1.7 V 2.35 2.9 3.5 V VCC=0.8 to 5.5V Vdet3s Low Voltage Reset Hold Vdet3r Low Voltage Reset Release Voltage Voltage(2) NOTES: 1. Vdet4 >Vdet3 2.
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M16C/29 Group 21. Electrical Characteristics (Normal-version) VCC = 5V Table 21.8 Electrical Characteristics (Note 1) Symbol VOH VOH Parameter Output High P00 to ("H") Voltage P70 to Output High P00 to ("H") Voltage P70 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67, IOH=-5mA P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107 P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67, IOH=-200µA VCC-0.3 VCC High Power IOH=-1mA VCC-2.0 VCC Low Power IOH=-0.5mA VCC-2.
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21. Electrical Characteristics (Normal-version) M16C/29 Group VCC = 5V Table 21.9 Electrical Characteristics (2) (Note 1) Symbol ICC Parameter Measurement Condition Power Supply Output pins are Mask ROM Current left open and (VCC=4.2 to 5.
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M16C/29 Group 21. Electrical Characteristics (Normal-version) VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 21.10 External Clock Input (XIN input) Symbol Parameter Standard Min. Max. Unit tc External Clock Input Cycle Time 50 ns tw(H) External Clock Input High ("H") Width 20 ns tw(L) External Clock Input Low ("L") Width 20 ns tr External Clock Rise Time 9 ns tf External Clock Fall Time 9 ns Rev. 1.
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21. Electrical Characteristics (Normal-version) M16C/29 Group VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 21.11 Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Max. Min. 100 Unit ns 40 ns 40 ns Table 21.
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M16C/29 Group 21. Electrical Characteristics (Normal-version) VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 21.17 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
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21. Electrical Characteristics (Normal-version) M16C/29 Group VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 21.23 Multi-master I2C bus Line Symbol Parameter Standard clock mode Min. Max. High-speed clock mode Min. Max. Unit tBUF Bus free time 4.7 1.3 µs tHD;STA The hold time in start condition 0.6 µs tLOW The hold time in SCL clock 0 status 4.0 4.7 1.3 20+0.
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M16C/29 Group 21.
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21. Electrical Characteristics (Normal-version) M16C/29 Group VCC = 5V tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) RxDi th(C–D) tw(INL) INTi input tw(INH) Figure 21.2 Timing Diagram (2) VCC = 5V SDA tHD:STA tBUF tLOW SCL p tR tF Sr S tHD:STA tHD:DTA Figure 21.3 Timing Diagram (3) Rev. 1.12 Mar.
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M16C/29 Group 21. Electrical Characteristics (Normal-version) VCC = 3V Table 21.24 Electrical Characteristics (Note 1) Symbol VOH Parameter Output High ("H") Voltage XOUT Output High ("H") Voltage XCOUT IOH = -1 mA High Power IOH = -0.1 mA VCC-0.5 VCC Low Power IOH = -50 µA VCC-0.5 VCC High Power No load applied 2.5 Low Power No load applied 1.
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21. Electrical Characteristics (Normal-version) M16C/29 Group VCC = 3V Table 21.25 Electrical Characteristics (2) (Note 1) Symbol ICC Parameter Measurement Condition Power Supply Current (VCC = 2.7 to 3.6V) Output pins are Mask ROM left open and other pins are connected to VSS f(BCLK) = 10 MHz, main clock, no division On-chip oscillation, f2(ROC) selected, f(BCLK) = 1 MHz Flash memory f(BCLK) = 10 MHz, main clock, no division Flash memory f(BCLK) = 10 MHz, Vcc = 3.
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M16C/29 Group 21. Electrical Characteristics (Normal-version) VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 21.26 External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 381 of 458 Standard Min. Max.
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21. Electrical Characteristics (Normal-version) M16C/29 Group VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 21.27 Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Max. Min. 150 60 60 Unit ns ns ns Table 21.
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M16C/29 Group 21. Electrical Characteristics (Normal-version) VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 21.33 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
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21. Electrical Characteristics (Normal-version) M16C/29 Group VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 21.39 Multi-master I2C bus Line Symbol Parameter Standard clock mode Min. Max. High-speed clock mode Min. Max. Unit tBUF Bus free time 4.7 1.3 µs tHD;STA The hold time in start condition 0.6 µs tLOW The hold time in SCL clock 0 status 4.0 4.
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M16C/29 Group 21.
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21. Electrical Characteristics (Normal-version) M16C/29 Group VCC = 3V tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) RxDi th(C–D) tw(INL) INTi input tw(INH) Figure 21.5 Timing Diagram (2) VCC = 3V SDA tHD:STA tBUF tLOW SCL p tR tF Sr S tHD:STA tHD:DTA Figure 21.6 Timing Diagram (3) Rev. 1.12 Mar.
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21. Electrical Characteristics (T-version) M16C/29 Group 21.2 T version Table 21.40 Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage AVCC Analog Supply Voltage VI Input Voltage Condition Value Unit VCC=AVCC -0.3 to 6.5 V VCC=AVCC -0.3 to 6.5 V -0.3 to VCC+0.3 V -0.3 to VCC+0.
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21. Electrical Characteristics (T-version) M16C/29 Group Table 21.41 Recommended Operating Conditions (Note 1) Symbol Standard Parameter Min. 3.0 Typ. Max. 5. 5 Unit VCC AVCC Supply Voltage Analog Supply Voltage VSS Supply Voltage 0 V AVSS Analog Supply Voltage 0 V VIH Input High ("H") Voltage VCC P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67, 0.7VCC P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107 0.
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21. Electrical Characteristics (T-version) M16C/29 Group Table 21.42 A/D Conversion Characteristics (Note 1) Symbol - Parameter Resolution Integral Nonlinearity Error INL Measurement Condition 10 bit 8 bit - Absolute Accuracy 10 bit 8 bit Standard Min. Typ. Max. Unit VREF = VCC 10 Bits VREF = VCC = 5 V ±3 LSB VREF = VCC = 3.3 V ±5 LSB VREF = VCC = 3.3 V ±2 LSB VREF = VCC = 5 V ±3 LSB VREF = VCC = 3.3 V ±5 LSB VREF = VCC = 3.
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21. Electrical Characteristics (T-version) M16C/29 Group Table 21.43 Flash Memory Version Electrical Characteristics (1) for 100/1000 E/W cycle products [Program Space and Data Space in U3; Program Space in U7] Symbol Standard Parameter - Program and Erase Endurance(3) - Word Program Time (VCC = 5.0 V, Topr = 25° C) - Block Erase Time (VCC = 5.0 V, Topr = 25° C) Min. Typ.(2) ( 4 , 1 100/1000 1) 75 Max. Unit cycles 600 0.2 9 2-Kbyte Block 0.4 9 8-Kbyte Block 0.7 9 16-Kbyte Block 1.
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21. Electrical Characteristics (T-version) M16C/29 Group Table 21.45 Power Supply Circuit Timing Characteristics Symbol Parameter Measurement Condition td(P-R) Wait Time to Stabilize Internal Supply Voltage when Power-on td(ROC) Wait Time to Stabilize Internal On-chip Oscillator when Power-on td(R-S) td(W-S) Standard Min. Typ. Max.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 5V Table 21.46 Electrical Characteristics (Note 1) Symbol VOH VOH Parameter Output High P00 to ("H") Voltage P70 to Output High P00 to ("H") Voltage P70 to P07, P77, P07, P77, P10 to P80 to P10 to P80 to P17, P87, P17, P87, P20 to P90 to P20 to P90 to Condition XOUT Output High ("H") Voltage XCOUT VOH VOL VOL Output Low P00 to ("L") Voltage P70 to Output Low P00 to ("L") Voltage P70 to IOH = -5 mA Typ. Max. VCC VCC-2.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 5V Table 21.47 Electrical Characteristics (2) (Note 1) Symbol ICC Parameter Measurement Condition Power Supply Output pins are Mask ROM Current left open and (VCC=4.2 to 5.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 21.48 External Clock Input (XIN input) Symbol Parameter Standard Min. Max. Unit tc External Clock Input Cycle Time 50 ns tw(H) External Clock Input High ("H") Width 20 ns tw(L) External Clock Input Low ("L") Width 20 tr External Clock Rise Time 9 ns tf External Clock Fall Time 9 ns Rev. 1.12 Mar.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 21.49 Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) Parameter TAiIN input cycle time Standard Max. Min. 100 tw(TAH) TAiIN input HIGH pulse width 40 tw(TAL) TAiIN input LOW pulse width 40 Unit ns ns ns Table 21.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 21.55 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 21.61 Multi-master I2C bus Line Symbol Parameter Standard clock mode Min. Max. High-speed clock mode Min. Max. Unit tBUF Bus free time 4.7 1.3 µs tHD;STA The hold time in start condition 4.0 4.7 0.
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21.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 5V tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) RxDi th(C–D) tw(INL) INTi input tw(INH) Figure 21.8 Timing Diagram (2) VCC = 5V SDA tHD:STA tBUF tLOW SCL p tR tF Sr S tHD:STA tHD:DTA Figure 21.9 Timing Diagram (3) Rev. 1.12 Mar.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 3V Table 21.62 Electrical Characteristics (Note) Symbol VOH Parameter Output High ("H") Voltage XOUT Output High ("H") Voltage XCOUT IOH = -1 mA High Power IOH = -0.1 mA VCC-0.5 VCC Low Power IOH = -50 µA VCC-0.5 VCC High Power No load applied 2.5 Low Power No load applied 1.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 3V Table 21.63 Electrical Characteristics (2) (Note 1) Symbol ICC Parameter Measurement Condition Power Supply Output pins are Mask ROM Current left open and (VCC=3.0 to 3.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 21.64 External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 402 of 458 Standard Min. Max.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 21.65 Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Max. Min. 150 60 60 Unit ns ns ns Table 21.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 21.71 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 21.77 Multi-master I2C bus Line Symbol Parameter Standard clock mode Min. Max. High-speed clock mode Min. Max. Unit tBUF Bus free time 4.7 1.3 µs tHD;STA The hold time in start condition µs The hold time in SCL clock 0 status 4.0 4.7 0.
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21.
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21. Electrical Characteristics (T-version) M16C/29 Group VCC = 3V tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) RxDi th(C–D) tw(INL) INTi input tw(INH) Figure 21.11 Timing Diagram (2) VCC = 3V SDA tHD:STA tBUF tLOW SCL p tR tF Sr S tHD:STA tHD:DTA Figure 21.12 Timing Diagram (3) Rev. 1.12 Mar.
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21. Electrical Characteristics (V-version) M16C/29 Group 21.3 V Version Table 21.78 Absolute Maximum Ratings Symbol Parameter Condition Value Unit VCC Supply Voltage VCC=AVCC -0.3 to 6.5 V AVCC Analog Supply Voltage VCC=AVCC -0.3 to 6.5 V VI Input Voltage -0.3 to VCC+0.3 V -0.3 to VCC+0.
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21. Electrical Characteristics (V-version) M16C/29 Group Table 21.79 Recommended Operating Conditions (1) Symbol Standard Parameter VCC AVCC Supply Voltage Analog Supply Voltage Min. 4.2 Typ. Max. 5. 5 VCC Unit V V VSS Supply Voltage 0 V AVSS Analog Supply Voltage 0 V VIH Input High ("H") Voltage P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67, P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107 0.7 VCC VCC V 0.
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21. Electrical Characteristics (V-version) M16C/29 Group Table 21.80 A/D Conversion Characteristics (1) Symbol - Parameter Resolution Integral Nonlinearity Error INL DNL - Measurement Condition Standard Min. Typ. Max.
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21. Electrical Characteristics (V-version) M16C/29 Group Table 21.81 Flash Memory Version Electrical Characteristics (1) for 100/1000 E/W cycle products [Program Space and Data Space in U3; Program Space in U7] Symbol Standard Parameter Min. Typ.(2) ( 4 , 1 100/1000 1) Max. Unit - Program and Erase Endurance(3) - Word Program Time (VCC = 5.0 V, Topr = 25° C) 75 600 µs - Block Erase Time (VCC = 5.0 V, Topr = 25° C) 0.2 0.4 0.7 1.
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21. Electrical Characteristics (V-version) M16C/29 Group Table 21.83 Power Supply Circuit Timing Characteristics Symbol Parameter Measurement Condition td(P-R) Wait Time to Stabilize Internal Supply Voltage when Power-on td(ROC) Wait Time to Stabilize Internal On-chip Oscillator when Power-on td(S-R) td(E-A) Standard Min. Typ. Max.
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21. Electrical Characteristics (V-version) M16C/29 Group VCC = 5V Table 21.84 Electrical Characteristics (1) Symbol VOH VOH Parameter Output High P00 to ("H") Voltage P70 to Output High P00 to ("H") Voltage P70 to P07, P77, P07, P77, P10 to P80 to P10 to P80 to P17, P87, P17, P87, P20 to P90 to P20 to P90 to Condition XOUT Output High ("H") Voltage XCOUT VOH VOL VOL Output Low P00 to ("L") Voltage P70 to Output Low P00 to ("L") Voltage P70 to IOH = -5 mA Typ. Max. VCC VCC-2.
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21. Electrical Characteristics (V-version) M16C/29 Group VCC = 5V Table 21.85 Electrical Characteristics (2) (1) Symbol ICC Parameter Measurement Condition Power Supply Output pins are Mask ROM Current left open and (VCC=4.2 to 5.
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21. Electrical Characteristics (V-version) M16C/29 Group VCC = 5V Timing Requirements (Vcc=5V, Vss=0V, at Topr=-40 to 125°C unless otherwise specified) Table 21.86 External Clock Input (XIN input) Symbol Standard Parameter tc External Clock Input Cycle Time tw(H) External Clock Input High ("H") Width tw(L) External Clock Input Low ("L") Width tr External Clock Rise Time tf External Clock Fall Time Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 415 of 458 Min. Max.
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21. Electrical Characteristics (V-version) M16C/29 Group VCC = 5V Timing Requirements (VCC=5V, VSS=0V, at Topr=-40 to 125°C unless otherwise specified) Table 21.87 Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. M ax . Unit tc(TA) TAiIN Input Cycle Time 100 ns tw(TAH) TAiIN Input High ("H") Width 40 ns tw(TAL) TAiIN Input Low ("L") Width 40 ns Table 21.88 Timer A Input (Gating Input in Timer Mode) Symbol Parameter Standard Min. M ax .
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21. Electrical Characteristics (V-version) M16C/29 Group VCC = 5V Timing Requirements (VCC=5V, VSS=0V, at Topr=-40 to 125°C unless otherwise specified) Table 21.93 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TB) TBiIN Input Cycle Time (counted on one edge) Standard Min. Max.
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21. Electrical Characteristics (V-version) M16C/29 Group VCC = 5V Timing Requirements (VCC=5V, VSS=0V, at Topr=-40 to 125°C unless otherwise specified) Table 21.99 Multi-master I2C Bus Line Symbol Parameter Standard clock mode Min. Max. High-speed clock mode Min. Max. Unit tBUF Bus free time 4.7 1.3 µs tHD;STA The hold time in start condition µs The hold time in SCL clock "0" status 4.0 4.7 0.6 tLOW 1.3 20+0.
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21.
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21. Electrical Characteristics (V-version) M16C/29 Group VCC = 5V tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) RxDi th(C–D) tw(INL) INTi input tw(INH) Figure 21.14 Timing Diagram (2) VCC = 5V SDA tHD:STA tBUF tLOW SCL p tR Sr tHD:DTA Figure 21.15 Timing Diagram (3) Rev. 1.12 Mar.
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22. Usage Notes M16C/29 Group 22. Usage Notes 22.1 SFRs 22.1.1 For 80-Pin Package Set the IFSR20 bit in the IFSR2A register to 0 after reset and set bits PACR2 to PACR0 in the PACR register to 0112. 22.1.2 For 64-Pin Package Set the IFSR20bit in the IFSR2A register to 0 after reset and set bits PACR2 to PACR0 in the PACR register to 0102. 22.1.3 Register Setting Immediate values should be set in the registers containing write-only bits.
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22. Usage Notes M16C/29 Group 22.2 Clock Generation Circuit 22.2.1 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. Symbol Standard Parameter Min. Typ. Max. Unit f(ripple) Power supply ripple allowable frequency(VCC) 10 kHz Vp-p(ripple) Power supply ripple allowabled amplitude voltage (VCC=5V) 0.5 V (VCC=3V) 0.3 V VCC(|DV/DT|) Power supply ripple rising/falling gradient (VCC=5V) 0.3 V/ms (VCC=3V) 0.
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22. Usage Notes M16C/29 Group 22.2.2 Power Control 1. When exiting stop mode by hardware reset, the device will startup using the on-chip oscillator. 2. Set the MR0 bit in the TAiMR register(i=0 to 4) to 0 (pulse is not output) to use the timer A to exit stop mode. 3. When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not excute any instructions which can generate a write to RAM between the JMP.B and WAIT instructions.
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22. Usage Notes M16C/29 Group 5. Wait until the main clock oscillation stabilization time, before switching the CPU clock source to the main clock. Similarly, wait until the sub clock oscillates stably before switching the CPU clock source to the sub clock. 6. Suggestions to reduce power consumption (a) Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports.
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22. Usage Notes M16C/29 Group 22.3 Protection Set the PRC2 bit to 1 (write enabled) and then write to any address, and the PRC2 bit will be cleared to 0 (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to 1. Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to 1 and the next instruction. Rev. 1.12 Mar.
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22. Usage Notes M16C/29 Group 22.4 Interrupts 22.4.1 Reading Address 0000016 Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to 0.
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22. Usage Notes M16C/29 Group Changing the interrupt source Disable interrupts (2,3) Change the interrupt generate factor (including a mode change of peripheral function) Use the MOV instruction to clear the IR bit to 0 (interrupt not requested) (3) Enable interrupts (2,3) End of change IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed NOTES: 1.The above settings must be executed individually.
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22. Usage Notes M16C/29 Group 22.4.6 Rewrite the Interrupt Control Register (1) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used.
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22. Usage Notes M16C/29 Group 22.5 DMAC 22.5.1 Write to DMAE Bit in DMiCON Register When both of the conditions below are met, follow the steps below. (a) Conditions • The DMAE bit is set to 1 again while it remains set (DMAi is in an active state). • A DMA request may occur simultaneously when the DMAE bit is being written. (b) Procedure (1) Write 1 to the DMAE bit and DMAS bit in DMiCON register simultaneously(1). (2) Make sure that the DMAi is in an initial state(2) in a program.
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22. Usage Notes M16C/29 Group 22.6 Timers 22.6.1 Timer A 22.6.1.1 Timer A (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to 1 (count starts). Always make sure the TAiMR register is modified while the TAiS bit remains 0 (count stops) regardless whether after reset or not. 2.
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22. Usage Notes M16C/29 Group 22.6.1.3 Timer A (One-shot Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).
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22. Usage Notes M16C/29 Group 22.6.1.4 Timer A (Pulse Width Modulation Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using bits TA0TGL and TA0TGH in the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).
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22. Usage Notes M16C/29 Group 22.6.2 Timer B 22.6.2.1 Timer B (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to 1 (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains 0 (count stops) regardless whether after reset or not. 2. The counter value can be read out at any time by reading the TBi register.
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22. Usage Notes M16C/29 Group 6. When a count is started and the first effective edge is input, an undefined value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. 7. A value of the counter is undefined at the beginning of a count. MR3 may be set to 1 and timer Bi interrupt request may be generated between a count start and an effective edge input. 8. For pulse width measurement, pulse widths are successively measured.
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22. Usage Notes M16C/29 Group 22.7 Timer S 22.7.1 Rewrite the G1IR Register Bits in the G1IR register are not automatically set to 0 (no interrupt requested) even if a requested interrupt is acknowledged. Set each bit to 0 by program after the interrupt requests are verified. The IC/OC interrupt is generated when any bit in the G1IR register is set to 1 (interrupt requested) after all the bits are set to 0.
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22. Usage Notes M16C/29 Group 22.7.2 Rewrite the ICOCiIC Register When the interrupt request to the ICOCiIC register is generated during the instruction process, the IR bit may not be set to 1 (interrupt requested) and the interrupt request may not be acknowledged. At that time, when the bit in the G1IR register is held to 1 (interrupt requested), the following IC/OC interrupt request will not be generated. When changing the ICOCiIC register settiing, use the following instruction.
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22. Usage Notes M16C/29 Group 22.8 Serial I/O 22.8.1 Clock-Synchronous Serial I/O 22.8.1.1 Transmission/reception _______ ________ 1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, ________ which informs the transmission side that the reception________ has become ready. The output level of the RTSi pin goes to “H” when reception ________ starts.
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22. Usage Notes M16C/29 Group 22.8.2 UART Mode 22.8.2.1 Special Mode 1 (I2C bus Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to 0 and wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ, RSTAREQ and STPREQ) from 0 to 1. 22.8.2.
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22. Usage Notes M16C/29 Group 22.9 A/D Converter 1. Set registers ADCON0 (except bit 6), ADCON1, ADCON2 and ADTRGCON when A/D conversion is stopped (before a trigger occurs). 2. When the VCUT bit in ADCON1 register is changed from 0 (Vref not connected) to 1 (Vref connected), start A/D conversion after passing 1 µs or longer. 3.
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22. Usage Notes M16C/29 Group 8. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU clock.
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22. Usage Notes M16C/29 Group 22.10 Multi-Master I2C bus Interface 22.10.1 Writing to the S00 Register When the start condition is not generated, the SCL pin may output the short low-signal ("L") by setting the S00 register. Set the register when the SCL pin outputs an "L" signal. 22.10.2 AL Flag When the arbitration lost is generated and the AL flag in the S10 register is set to 1 (detected), the AL flag can be cleared to 0 (not detected) by writing a transmit data to the S00 register.
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22. Usage Notes M16C/29 Group 22.11 CAN Module 22.11.1 Reading C0STR Register The CAN module on the M16C/29 Group updates the status of the C0STR register in a certain period. When the CPU and the CAN module access to the C0STR register at the same time, the CPU has the access priority; the access from the CAN module is disabled. Consequently, when the updating period of the CAN module matches the access period from the CPU, the status of the CAN module cannot be updated. (See Figure 22.
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22. Usage Notes M16C/29 Group fCAN CPU read signal Updating period of CAN module CPU reset signal C0STR register ✕ b8: State_Reset bit 0: CAN operation mode 1: CAN reset/initialization mode ✕ ✕ ✕ ✕ ✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read period, it does not enter reset mode, for the CPU read has the higher priority. Figure 22.
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22. Usage Notes M16C/29 Group 22.11.2 CAN Transceiver in Boot Mode When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be set to “high-speed mode” or “normal operation mode”. If the operation mode is controlled by the MCU, CAN transceiver must be set the operation mode to “high-speed mode” or “normal operation mode” before programming the flash memory by changing the switch etc. Tables 22.3 and 22.4 show pin connections of CAN transceiver. Table 22.
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22. Usage Notes M16C/29 Group 22.12 Programmable I/O Ports _____ 1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to 1 _____ (three-phase output forcible cutoff by input on SD pin enabled), the P72 to P75, P80 and P81 pins go to a high-impedance state. 2. The input threshold voltage of pins differs between programmable input/output ports and peripheral functions.
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22. Usage Notes M16C/29 Group 22.13 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the flash memory version. Rev. 1.12 Mar.
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22. Usage Notes M16C/29 Group 22.14 Mask ROM Version 22.14.1 Internal ROM Area In the masked ROM version, do not write to internal ROM area. Writing to the area may increase power consumption. 22.14.2 Reserved Bit The b3 to b0 in addresses 0FFFFF16 are reserved bits. Set these bits to 11112. Rev. 1.12 Mar.
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22. Usage Notes M16C/29 Group 22.15 Flash Memory Version 22.15.1 Functions to Inhibit Rewriting Flash Memory Rewrite ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode. The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash memory cannot be read or written in parallel I/O mode.
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22. Usage Notes M16C/29 Group 22.15.9 Interrupts EW Mode 0 • Any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the RAM area. _______ • The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs. The jump addresses for those interrupt service routines should be set in the fixed vector table.
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22. Usage Notes M16C/29 Group 22.15.14 Definition of Programming/Erasure Times "Number of programs and erasure" refers to the number of erasure per block. If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times. For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different address, this is counted as one program and erasure. However, data cannot be written to the same adrress more than once without erasing the block.
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22. Usage Notes M16C/29 Group 22.16 Noise Connect a bypass capacitor (approximately 0.1µF) across the VCC and VSS pins using the shortest and thicker possible wiring. Figure 22.8 shows the bypass capacitor connection. M16C/29 Group VSS VCC Connecting Pattern Connecting Pattern Bypass Capacitor Figure 22.8 Bypass Capacitor Connection Rev. 1.12 Mar.
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22. Usage Notes M16C/29 Group 22.17 Instruction for a Device Use When handling a device, extra attention is necessary to prevent it from crashing during the electrostatic discharge period. Rev. 1.12 Mar.
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Appendix 1. Package Dimensions M16C/29 Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 D NOTE) 1. *2" 2. INCLUDE TRIM OFFSET. c1 Reference Symbol c E *2 HE p D E A HD ZE Terminal cross section E A A1 Z p b1 c c1 c A1 A A2 F e x y ZD ZE L L1 L L1 Detail F JEITA Package Code P-LQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A Min Nom Max 9.9 10.
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Appendix 2. Functional Comparison M16C/29 Group Appendix 2. Functional Comparison Appendix 2.1 Difference between M16C/28 Group and M16C/29 Group (Normal-ver.) (1) Item Description Clock Generation Circuit M16C/28(Normal-ver.) M16C/29(Normal-ver.
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Appendix 2. Functional Comparison M16C/29 Group Appendix 2.2 Difference between M16C/28 and M16C/29 Group (T-ver./V-ver.) (1) Item Description Protection Interrupt CAN module Pin Function I: Input M16C/28(T-ver./V-ver.) M16C/29(T-ver./V-ver.
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Register Index M16C/29 Group Register Index A AD0 to AD7 226 ADCON0 to ADCON2 224 ADIC 76 ADSTAT0 226 ADTRGCON 225 AIER 88 F FMR0 341 FMR1 341 FMR4 342 B BCNIC 76 BTIC 76 G C G1BCR0 142 G1BCR1 143 G1BT 142 G1BTRR 144 G1DV 143 G1FE 148 G1FS 148 G1IE0 150 G1IE1 150 G1IR 149 G1PO0 to G1PO7 147 G1POCR0 to G1POCR7 146 G1TM0 to G1TM7 146 G1TMCR0 to G1TMCR7 145 G1TPR6 to G1TPR7 145 C01ERRIC 76 C01WKIC 76 C0AFS 299 C0CONR 297 C0CTLR 293 C0ICR 296 C0IDR 296 C0MCTLj 292 C0RECIC 76 C0RECR 298 C0SSTR 295 C0STR
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Register Index M16C/29 Group S4BRG 218 S4C 218 S4D0 262 S4IC 76 S4TRR 218 SAR0 95 SAR1 95 SCLDAIC 76 K KUPIC 76 N NDDR 327 O ONSF 105 T P TA0 to TA4 104 TA0IC to TA4IC 76 TA0MR to TA4MR 103 TA11 130 TA1MR 133 TA2 130 TA21 130 TA2MR 133 TA4 130 TA41 130 TA4MR 133 TABSR 104, 118, 132 TB0 to TB2 118 TB0IC to TB2IC 76 TB0MR to TB2MR 117 TB2 132 TB2MR 133 TB2SC 131, 227 TCR0 95 TCR1 95 TPRC 139 TRGSR 105, 132 P0 to P3 324 P17DDR 327 P6 to P10 324 PACR 177, 326 PCLKR 52 PCR 326 PD0 to PD3 323 PD6 to PD10
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Register Index M16C/29 Group V VCR1 39 VCR2 39 W WDC 90 WDTS 90 Rev. 1.12 Mar.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 0.70 Mar/ 29/Y04 1 2, 3 8, 9 10 22 28 30 31 32 36 37 38 39 40 41 42 45 46 54 57 64 65 66 67 68 73 74 94 102 106 111 112 115 117 119 “1. Overview” and “1.1. Application” are partly revised. Table 1.2.1 and 1.2.2 are partly revised. Figure 1.5.1 and 1.5.2 are partly revised. Table 1.6.1 is revised. Figure 4.8 is partly revised. Section “5.5 Voltage Detection Circuit” and Figure 5.5.2 are partly revised. Figure 5.5.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 122 125 126 “Figure 12.3.9 PFCR register and TPRC register” is deleted. Figure 12.3.1.2.1 and the section 12.3.1.2.4 are partly revised. Section “Three-phase/Port Output Switch Function” and “Figure 12.3.2.1 PFCR register and TPRC register” are added. 166 “UART 2 special mode register 2” in Figure 14.1.8 is partly revised. 167 “UART 2 special mode register 3” in Figure 14.1.9 is partly revised. 210 Note 1 in Table 15.1.1.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 399 400 403 404 405 406 407 0.71 April/15/Y04 B-1 to B-3 B-4, B-5 2,3 6,7 14 15 to 20 21, 22, 25 29 33 34 40 64 65 112 119 126 130 134 137 162 170 177 184 214 230, 231 233 235 236, 237 240 244 321 342 Figure 21.9.1 is partly revised. Figure 21.9.2 is partly revised. Section “21.10.1 ROM Code Protect Function” is partly revised. Section “21.11.1 ROM Code Protect Function” is partly revised. Table 21.11.1 is revised. Figure 21.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 360 368 0.80 Sep/03/Y04 2,3 6,7 7 8,9 21 24 26 29 to 34 80 322 323 325 327 331 335 339 343 344 346 Table 21.1 is partly revised. Section “21.4.2 EW1 Mode” is partly revised. Table 1.2.1 and Table 1.2.2 are partly revised. Table 1.4.1 to Table 1.4.3 are partly revised. Figure 1.4.1 is partly revised. Figure 1.5.1 and Figure 1.5.2 are partly revised. Figure 4.7 is partly revised. Figure 4.10 is partly revised. Section “5.1.
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REVISION HISTORY Rev. Date 1.10 10/10/06 M16C/29 Hardware Manual Description Page Summary 66 “9.3 Interrupt Control” is partly revised. ______ _______ 76 “9.6 INT Interrupt” and “9.7 NMI Interrupt” are partly revised. 77 “9.8 Key Input Interrupt” and “9.9 CAN0 Wake-up Interrupt” are partly revised. 80 “10. Watchdog Timer” is partly revised. 80, 81 “10.1 Count source protective mode” is partly revised. 81 Note 2 in Figure 10.2 is revised. 118 Figure 12.3.1 is partly revised.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 2 4-5 6-7 8 9 13 - 17 18 23 24 - 34 24 35 38 44 45 46 47 48 50 52 54 55 59 60 61 Overview • Table 1.1 and 1.2 Performance Outline Voltage detection circuit are modified, note 3 is modified • Figure 1.1 and 1.2 Block Diagrams are updated • Table 1.3 to 1.5 Product Lists are updated • Figure 1.3 Produt Numbering System is modified • Tables 1.6 to 1.8 Product Code B3, B7, D3, D5, D7, D9 are deleted • Tables 1.9 to 1.
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REVISION HISTORY Rev. Date M16C/29 Hardware Manual Description Page Summary 63 • Figure 7.11 State Transition to Stop Mode and Wait Mode modified, Note 7 is added 64 • Figure 7.12 State Transition in Normal Mode modified, note 5 deleted, note 6 and 7 are simplified 65 • Table 7.7 Allowed Transition and Setting note 2 partially modified, table con tents are partially modified 68 • Figure 7.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 160 166 167 168 170 171 174 175 176 177 180 182 183 184 185 186 187 188 190 192 193 195 196 note 1 is added • Figure 13.21 Prescaler Function and Gate Function Note 1 modified • Table 13.10 SR Waveform Output Mode Specifications Specification modified • Figure 13.24 Set/Reset Waveform Output Mode Description for (1) Free-running operation modified, register names modified • Table 13.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 214 217 218 220 221 222 224 227 229 231 233 235 237 239 241 245 251 254 255 256 257 • Figure 14.31 Transmit and Received Timing in SIM Mode partially modified • 14.2 SI/O3 and SI/O4 Note added • Figure 14.36 S3C and S4C Registers Note 5 is added • Figure 14.36 S3BRG and S4BRG Registers Note 3 is added • Figure 14.38 Polarity of Transfer Clock figure modified • 14.2.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 258 259 260 262 269 270 • Figure 16.3 S00 Register Note is modified • Figure 16.4 S1D0 Register Reserved bit map modified • Figure 16.5 S10 Register b7-b6 modified • Figure 16.7 S4D0 Register Bit reserved map is modified • 16.5.1 Bit 0: Last Receive Bit (LRB) modified • 16.5.2 Bit 1: General call detection flag (ADR0) modified, note 1 modified • 16.5.3 Bit 2: Slave address comparison flag (AAS) modified • 16.5.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 329 330 331 332 335 336 337 339 340 341 342 345 346 352 355 366 367 368 369 370 372 380 387 • Table 19.1 Unassigned Pin Handling in Single-chip Mode Note 5 added Flash Memory Version • 20.1 Flash Memory Performance Description partially deleted • Table 20.14 Flash Memory Version Specifications Note 3 added • 20.1.1 Boot Mode added • 20.2 Memory Map Description is modified • 20.3.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 388 389 390 391 393 401 422 423 425 426 427 431 434 435 436 438 441 445 447 448 449 450 • Table 21.41 Recommended Operating Conditions VIH and VIL are modified • Table 21.42 A/D Conversion Characeristics tSAMP deleted, note 4 added • Table 21.43 Flash Memory Version Electrical Characteristics: Standard values of Program and Erase Endrance cycle modified, tps added • Table 21.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page products (U7, U9) added • 22.15.16 Boot Mode added 451 • 22.16 Noise added 452 • 20.17 Instruction fo Device Use added Appendix 1. Package Dimensions 453 • Dimensions are updated 454-455 Appendix 2. Functional Comparison added 1.11 Dec.11,2006 Clock Generation Circuit 54 • Figure 7.8 Examples of Main Clock Connection Circuit Note 2 added Interrupts 88 • Table 9.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 9 19, 20 37 45 52 64 69 88 90 129 256 335 340 341 343 369 370 372 380 390 391 393 • Tables 1.6 to 1.8 Product Codes modified • Table 1.14 Pin Description pin description on I/O ports modified Reset • Figure 5.2 Reset Sequence Vcc and ROC timings modified Processor Mode • Figure 6.2 PM2 Register Description on notes 5 and 6 modified Clock Generation Circuit • Figure 7.
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REVISION HISTORY Rev. M16C/29 Hardware Manual Date Description Summary Page 401 411 412 414 439 449 450 4 deleted • Table 21.63 Elctrical Characteristics measurement condition modified, note 4 deleted •Tables 21.81 and 21.82 Flash Memory Version Electrical Characteristics note 10 modified •Timing figure for td(P-R) and td(ROC) modified •Table 21.85 Electrical Characteristics measurment condition modified, note 4 deleted Usage Notes •Figure 22.4 Use of Capacitors to Reduce Noise note 1 modified •22.15.
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RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M16C/29 Group Publication Data : Rev.0.70 Mar. 29, 2004 Rev.1.12 Mar. 30, 2007 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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M16C/29 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0101-0112