Datasheet

1. Overview
page 4
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1.3 Block Diagram
Figure 1.1 is a block diagram of the M16C/28 Group (M16C/28, M16C/28B), 80-pin and 85-pin package.
Figure 1.2 is a block diagram of the M16C/28 Group (M16C/28, M16C/28B), 64-pin package.
Figure 1.1 M16C/28 Group (M16C/28, M16C/28B), 80-Pin/85-Pin Block Diagram
Output (Timer A) : 5
Input (Timer B) : 3
Internal Peripheral Functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
Memory
ROM
(1)
RAM
(2)
A/D converter
(10 bits x 24 channels)
UART/clock synchronous SI/O
(8 bits x 3 channels)
System clock generator
X
IN-XOUT
XCIN-XCOUT
On-chip oscillator
PLL frequency synthesizer
M16C/60 Series CPU Core
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
SB
ISP
USP
INTB
Multiplier
8
Port P10
7
Port P9
8
Port P8
Port P7
8
Port P6
8
Port P2
8
PC
FLG
Timer (16 bits)
3-phase PWM
Port P3
8
Port P1
8
I/O Ports
Port P0
8
Clock synchronous SI/O
(8 bits x 2 channels)
Multi-master I
2
C bus
(
)
Timer S
Input capture/
Output compare
Time measurement : 8 channels
Waveform generating : 8 channels
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.