Datasheet

1. Overview
page 16
33fo6002,51.peS05.0.veR
)B82/C61M,82/C61M(puorG82/C61M
Figure 1.6 Pin Assignment (Top View) of 64-Pin Package
Package: PLQP0064KB-A(64P6Q-A)
32
31
30
29
28
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
27
64
48
47
46
45
43
42
41
40
39
38
37
36
35
34
33
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P0
3
/AN0
3
P1
5
/INT
3
/AD
TRG
/IDV
P1
6
/INT
4
/IDW
P1
7
/INT
5
/INPC1
7
/IDU
P2
0
/OUTC1
0
/INPC1
0
/SDA
MM
P2
1
/OUTC1
1
/INPC1
1
/SCL
MM
P2
2
/OUTC1
2
/INPC1
2
P2
5
/OUTC1
5
/INPC1
5
P2
3
/OUTC1
3
/INPC1
3
P2
4
/OUTC1
4
/INPC1
4
P2
6
/OUTC1
6
/INPC1
6
P6 6 /RxD 1
P3 0 /CLK 3
P3 1 /S IN3
P3 2 /S OUT3
P3 3
P6 4 /CTS 1 /RTS 1 /CTS0/CLKS1
P6
5 /CLK 1
P6 7 /TxD 1
P7 0 /TxD 2 /SDA 2 /TA0 OUT /RTS1/CTS1/CTS0/CLKS1
P7
1 /RxD 2 /SCL 2 /TA0 IN /CLK1
P7
6 /TA3 OUT
P7 4 /TA2 OUT /W
P7
5 /TA2 IN /W
P7
2 /CLK 2 /TA1 OUT /V/RxD1
P7
3 /CTS 2 /RTS 2 /TA1 IN /V/TxD1
P0 0 /AN0 0
P10 7 /AN 7 /KI 3
P10 4 /AN 4 /KI 0
P10 3 /AN 3
P10 2 /AN 2
P10 1 /AN 1
AV SS
P10 0 /AN 0
V REF
AV CC
P9 3 /AN2 4
P9 2 /TB2 IN
P0 2 /AN0 2
P0 1 /AN0 1
P10 6 /AN 6 /KI 2
P10 5 /AN 5 /KI 1
P9
0
/TB0
IN
CNV
SS
P8
7
/X
CIN
P8
6
/X
COUT
RESET
X
OUT
X
IN
V
CC
P8
4
/INT
2
/ZP
P8
5
/NMI/SD
P8
1
/TA4
IN
/U
P8
0
/TA4
OUT
/U
P7 7 /TA3 IN
P9
1
/TB1
IN
P8
3
/INT
1
V
SS
P2
7
/OUTC1
7
/INPC1
7
P6
0
/CTS
0
/RTS
0
P6
1
/CLK
0
P6
2
/RxD
0
P6
3
/TxD
0
P8
2
/INT
0
NOTES:
1.Set PACR2 to PACR0 bit in the PACR register to "010
2" before you
input and output it after resetting to each pin. When the PACR
register isn't set up, the input and output function of some of the pins
are disabled.