Datasheet
1. Overview
page 13
33fo6002,51.peS05.0.veR
)B82/C61M,82/C61M(puorG82/C61M
Package: PLQP0080KB-A(80P6Q-A)
Figure 1.5 Pin Assignment (Top View) of 80-Pin Package
1 2 3 4 5 6 7 8 91011121314151617181920
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41424344454647484950515253545557585960
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
56
P6
1
/CLK
0
P3
5
P3
4
P3
3
P3
2
/SOUT
3
P3
1
/SIN
3
P3
7
P6
7
/T
X
D
1
P7
1
/RXD
2
/SCL
2
/TA0
IN
/CLK1
P7
2
/CLK
2
/TA1
OUT
/V/RxD1
P7
3
/CTS
2
/RTS
2
/TA1
IN
/V/TxD1
P6
5
/CLK
1
P6
6
/RxD
1
P6
4
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
P7
0
/TXD
2
/SDA
2
/TA0
OUT
/CTS1/RTS1/CTS
0
/CLKS
1
P7
5
/TA2
IN
/W
P3
0
/CLK
3
P7
4
/TA2
OUT
/W
P1
0
/AN2
0
P1
1
/AN2
1
P1
2
/AN2
2
P1
5
/INT
3
/AD
TRG
/IDV
P1
6
/INT
4
/IDW
P1
7
/INT
5
/INPC1
7
/IDU
P2
0
/OUTC1
0
/INPC1
0
/SDA
MM
P2
1
/OUTC1
1
/INPC1
1
/SCL
MM
P2
2
/OUTC1
2
/INPC1
2
P2
3
/OUTC1
3
/INPC1
3
P2
4
/OUTC1
4
/INPC1
4
P2
5
/OUTC1
5
/INPC1
5
P2
6
/OUTC1
6
/INPC1
6
P2
7
/OUTC1
7
/INPC1
7
P6
0
/CTS
0
/RTS
0
V
CC
X
IN
X
OUT
V
SS
RESET
CNVss
P8
7
/X
CIN
P8
6
/X
COUT
P7
6
/TA3
OUT
P7
7
/TA3
IN
P9
2
/TB2
IN
P9
3
/AN2
4
P9
5
/AN2
5
/CLK
4
P9
1
/TB1
IN
P8
2
/INT
0
P8
3
/INT
1
P8
1
/TA4
IN
/U
P8
4
/INT
2
/ZP
P8
0
/TA4
OUT
/U
P8
5
/NMI/SD
P0
0
/AN0
0
P0
1
/AN0
1
P0
2
/AN0
2
P0
3
/AN0
3
P0
4
/AN0
4
P0
5
/AN0
5
P0
6
/AN0
6
P0
7
/AN0
7
V
REF
AV
SS
AVcc
P10
0
/AN
0
P10
1
/AN
1
P10
2
/AN
2
P10
3
/AN
3
P10
4
/AN
4/
KI
0
P10
5
/AN
5
/KI
1
P10
6
/AN
6
/KI
2
P10
7
/AN
7
/KI
3
P9
6
/AN2
6
/SOUT
4
P9
7
/AN2
7
/SIN
4
P9
0
/TB0
IN
P6
3
/T
X
D
0
P6
2
/RxD
0
P3
6
P1
3
/AN2
3
P1
4
NOTES:
1.Set PACR2 to PACR0 bit in the PACR register to "011
2
" before you
input and output it after resetting to each pin. When the PACR
register isn't set up, the input and output function of some of the pins
are disabled.