Datasheet

13. Serial I/O
page 138
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Figure 13.1.6. U0C0 to U2C0 registers and UCON register
UARTi Transmit/receive Control Rregister 0 (i=0 to 2)
Symbol Address After Reset
U0C0 to U2C0 03A4
16 , 03AC 16 , 037C 16 00001000 2
b7 b6 b5 b4 b3 b2 b1 b0
Function
TXEPT
CLK1
CLK0
CRS
CRD
NCH
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
CLK polarity select bit
CTS/RTS function
select bit
CTS/RTS disable bi
t
Data output select bit
(5)
0 0 : f 1SIO or f 2SIO is selected
0 1 : f
8SIO is selected
1 0 : f
32SIO is selected
1 1 : Do not set
b1 b0
0 : LSB first
1 : MSB first
0 : Data in transmit register (during transmission)
1 : No data in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6
0 , P6 4 and P7 3 can be used as I/O ports)
(6)
0 : TxDi/SDA2 and SCL2 pins are CMOS output
1 : TxDi/SDA2 and SCL2 pins are N-channel open-drain output
(4)
UFORM Transfer format select bit
(2)
Effective when CRD is set to "0"
0 : CTS function is selected
(1)
1 : RTS function is selected
Bit Name
Bit
Symbol
NOTES:
1. Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
2. Effective when the SMD2 to SMD0 bits in the UMR register to "001
2 "(clock synchronous serial I/O mode) or "010 2 " (UART mode
transfer data 8 bits long). Set the UFORM bit to "1" when the SMD2 to SMD0 bits are set to "101
2 " (I
2
C bus mode) and "0" when
they are set to"100
2 " (UART mode transfer data 7 bits long) or "110 2 " ( UART mode transfer data 9 bits long).
3. CTS
1 /RTS 1 can be used when the CLKMD1 bit in the UCON register is set to “0” (only CLK 1 output) and the RCSP bit in the
UCON register is set to “0” (CTS
0 /RTS 0 not separated).
4. SDA2 and SCL2 are effective when i = 2.
5. When the SMD2 to SMD0 bits in UiMR regiser are set to “000
2 ” (serial I/O disable), do not set NCH bit to “1” (TxDi/SDA2 and
SCL2 pins are N-channel open-drain output).
6. When the U1MAP bit in PACR register is “1” (P7
3 to P7 0 ), CTS/RTS pin in UART1 is assigned to P7 0 .
7. When the CLK1 and CLK0 bit settings are changed, set the UiBRG register.
RW
RW
RW
RW
RW
RW
RW
RW
RO
(3)
(7)
UART Transmit/receive Control Register 2
Symbol Address After Reset
UCON 03B0
16 X0000000 2
b7 b6 b5 b4 b3 b2 b1 b0
Bit NameBit Symbol RWFunction
CLKMD0
CLKMD1
UART0 transmit interrupt
cause select bit
UART0 continuous
receive mode enable bit
0: Continuous receive mode disabled
1: Continuous receive mode enable
UART1 continuous
receive mode enable bit
UART1 CLK/CLKS
select bit 0
UART1 transmit interrupt
cause select bit
0: Transmit buffer empty (Tl = 1)
1: Transmission completed (TXEPT = 1)
0: Transmit buffer empty (Tl = 1)
1: Transmission completed (TXEPT = 1)
0: Continuous receive mode disabled
1: Continuous receive mode enabled
Nothing is assigned. When write, set to “0”.
When read, the content is indeterminate
U0IRS
U1IRS
U0RRM
U1RRM
UART1 CLK/CLKS
select bit 1
(1)
Effective when CLKMD1 bit is set to “1”
0: Clock output from CLK1
1: Clock output from CLKS1
RCSP
Separate UART0
CTS/RTS bit
(b7)
RW
RW
RW
RW
RW
RW
RW
NOTES:
1. To use more than one transfer clock output pins, set the CKDIR bit in the U1MR register to “0” (internal clock).
2. When the U1MAP bit in PACR register is set to “1” (P7
3 to P7 0 ), CTS 0 is supplied from the P7 0 pin.
0: Output from CLK1 only
1: Transfer clock output from multiple
pins function selected
0: CTS/RTS shared pin
1: CTS/RTS separated (CTS
0 supplied
from the P6
4 pin) (2)