Datasheet

10. Watchdog Timer
page 80
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For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer
period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that
the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start
counting by writing to the WDTS register.
Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the
beginning of the watchdog timer interrupt routine.
In stop mode, wait mode and when erase/program opration is excuting in EW1 mode without erase suspend
requeired, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the
modes or state are released.
Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related registers.
With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock
Watchdog timer period =
With sub-clock chosen for CPU clock
Watchdog timer period =
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
CPU clock
Prescaler dividing (2) X Watchdog timer count (32768)
CPU clock
Figure 10.1. Watchdog Timer Block Diagram
10. Watchdog Timer
The watchdog timer is the function that detects when a program is out of control. Use the watchdog timer is
recommended to improve reliability of the system. The watchdog timer contains a 15-bit counter which is
decremented by the CPU clock that the prescaler divides. The PM12 bit in the PM1 register determines whether
to generate a watchdog timer interrupt request or reset the watchdog timer when the watchdog timer underflows.
The PM12 bit can only be set to “1” (reset). Once the PM12 bit is set to “1”, it cannot be changed to “0” (watchdog
timer interrupt) by program. Refer to “5.3 Watchdog Timer Reset” for watchdog timer reset.
When the main clock, on-chip oscillator clock, or PLL clock runs as CPU clock, the WDC7 bit in the WDC register
determines whether the prescaler divides the clock by 16 or 128. When the sub clock runs as CPU clock, the
prescaler divides the clock by 2 regardless of the WDC7 bit setting. Watchdog timer cycle is calculated as
follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.
CPU clock
Write to WDTS register
PM12 = 0
Watchdog timer
Set to 7FFF 16
1/128
1/16
CM07 = 0
WDC7 = 1
CM07 = 0
WDC7 = 0
CM07 = 1
1/2
Prescaler
PM12 = 1
Reset
PM22 = 0
PM22 = 1
On-chip oscillator clock
Internal reset signal
(low active)
Watchdog timer
interrupt request