Datasheet

9. Interrupt
page 79
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 9.9.1. AIER Register, RMAD0 and RMAD1 Registers
Bit nameBit symbol
Symbol Address After reset
AIER 0009
16 XXXXXX00 2
Address match interrupt enable register
Function
RW
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
Symbol Address After reset
RMAD0 0012
16 to 0010 16 X00000 16
RMAD1 0016 16 to 0014 16 X00000 16
b7 b6 b5 b4 b3 b2 b1 b0
Address setting register for address match interrupt
Function Setting range
Address match interrupt register i (i = 0 to 1)
00000 16 to FFFFF 16
0 : Interrupt disabled
1 : Interrupt enabled
b0 b7 b0b3
(b19) (b16)
b7 b0
(b15) (b8)
b7
(b23)
RW
RW
(b7-b2)
RW
RW
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.